f2bc21ca1e| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rv_dm_smoke | 5.450s | 4.458ms | 2 | 2 | 100.00 |
| V1 | jtag_dtm_csr_hw_reset | rv_dm_jtag_dtm_csr_hw_reset | 3.150s | 1.005ms | 5 | 5 | 100.00 |
| V1 | jtag_dtm_csr_rw | rv_dm_jtag_dtm_csr_rw | 2.670s | 761.518us | 20 | 20 | 100.00 |
| V1 | jtag_dtm_csr_bit_bash | rv_dm_jtag_dtm_csr_bit_bash | 49.270s | 18.620ms | 5 | 5 | 100.00 |
| V1 | jtag_dtm_csr_aliasing | rv_dm_jtag_dtm_csr_aliasing | 1.610s | 830.770us | 5 | 5 | 100.00 |
| V1 | jtag_dmi_csr_hw_reset | rv_dm_jtag_dmi_csr_hw_reset | 29.220s | 12.460ms | 5 | 5 | 100.00 |
| V1 | jtag_dmi_csr_rw | rv_dm_jtag_dmi_csr_rw | 32.220s | 15.340ms | 20 | 20 | 100.00 |
| V1 | jtag_dmi_csr_bit_bash | rv_dm_jtag_dmi_csr_bit_bash | 5.236m | 137.092ms | 20 | 20 | 100.00 |
| V1 | jtag_dmi_csr_aliasing | rv_dm_jtag_dmi_csr_aliasing | 1.324m | 37.697ms | 5 | 5 | 100.00 |
| V1 | jtag_dmi_cmderr_busy | rv_dm_cmderr_busy | 1.560s | 442.582us | 2 | 2 | 100.00 |
| V1 | jtag_dmi_cmderr_not_supported | rv_dm_cmderr_not_supported | 1.580s | 636.234us | 2 | 2 | 100.00 |
| V1 | cmderr_exception | rv_dm_cmderr_exception | 1.400s | 187.992us | 2 | 2 | 100.00 |
| V1 | mem_tl_access_resuming | rv_dm_mem_tl_access_resuming | 1.360s | 256.166us | 0 | 2 | 0.00 |
| V1 | mem_tl_access_halted | rv_dm_mem_tl_access_halted | 1.520s | 541.592us | 2 | 2 | 100.00 |
| V1 | cmderr_halt_resume | rv_dm_cmderr_halt_resume | 2.690s | 1.265ms | 2 | 2 | 100.00 |
| V1 | dataaddr_rw_access | rv_dm_dataaddr_rw_access | 1.010s | 186.761us | 2 | 2 | 100.00 |
| V1 | halt_resume | rv_dm_halt_resume_whereto | 2.060s | 1.162ms | 8 | 8 | 100.00 |
| V1 | progbuf_busy | rv_dm_cmderr_busy | 1.560s | 442.582us | 2 | 2 | 100.00 |
| V1 | abstractcmd_status | rv_dm_abstractcmd_status | 1.340s | 239.179us | 2 | 2 | 100.00 |
| V1 | progbuf_read_write_execute | rv_dm_progbuf_read_write_execute | 2.330s | 1.028ms | 2 | 2 | 100.00 |
| V1 | progbuf_exception | rv_dm_cmderr_exception | 1.400s | 187.992us | 2 | 2 | 100.00 |
| V1 | rom_read_access | rv_dm_rom_read_access | 0.930s | 188.618us | 2 | 2 | 100.00 |
| V1 | csr_hw_reset | rv_dm_csr_hw_reset | 2.100s | 557.681us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_dm_csr_rw | 2.380s | 351.059us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_dm_csr_bit_bash | 36.830s | 6.725ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_dm_csr_aliasing | 52.710s | 4.370ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_dm_csr_mem_rw_with_rand_reset | 3.940s | 291.399us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_dm_csr_aliasing | 52.710s | 4.370ms | 5 | 5 | 100.00 |
| rv_dm_csr_rw | 2.380s | 351.059us | 20 | 20 | 100.00 | ||
| V1 | mem_walk | rv_dm_mem_walk | 1.070s | 169.560us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | rv_dm_mem_partial_access | 0.990s | 152.449us | 5 | 5 | 100.00 |
| V1 | TOTAL | 178 | 180 | 98.89 | |||
| V2 | idcode | rv_dm_smoke | 5.450s | 4.458ms | 2 | 2 | 100.00 |
| V2 | jtag_dtm_hard_reset | rv_dm_jtag_dtm_hard_reset | 1.400s | 392.075us | 2 | 2 | 100.00 |
| V2 | jtag_dtm_idle_hint | rv_dm_jtag_dtm_idle_hint | 2.090s | 746.362us | 2 | 2 | 100.00 |
| V2 | jtag_dmi_failed_op | rv_dm_dmi_failed_op | 1.570s | 287.478us | 2 | 2 | 100.00 |
| V2 | jtag_dmi_dm_inactive | rv_dm_jtag_dmi_dm_inactive | 3.790s | 1.806ms | 2 | 2 | 100.00 |
| V2 | sba | rv_dm_sba_tl_access | 13.224m | 300.000ms | 0 | 20 | 0.00 |
| rv_dm_delayed_resp_sba_tl_access | 14.504m | 300.000ms | 0 | 20 | 0.00 | ||
| V2 | bad_sba | rv_dm_bad_sba_tl_access | 13.468m | 300.000ms | 0 | 20 | 0.00 |
| V2 | sba_autoincrement | rv_dm_autoincr_sba_tl_access | 13.923m | 300.000ms | 0 | 20 | 0.00 |
| V2 | jtag_dmi_debug_disabled | rv_dm_jtag_dmi_debug_disabled | 1.670s | 406.544us | 0 | 2 | 0.00 |
| V2 | sba_debug_disabled | rv_dm_sba_debug_disabled | 3.300s | 1.536ms | 2 | 2 | 100.00 |
| V2 | ndmreset_req | rv_dm_ndmreset_req | 1.500s | 385.987us | 2 | 2 | 100.00 |
| V2 | hart_unavail | rv_dm_hart_unavail | 1.730s | 334.836us | 0 | 5 | 0.00 |
| V2 | tap_ctrl_transitions | rv_dm_tap_fsm | 5.730s | 5.361ms | 1 | 1 | 100.00 |
| rv_dm_tap_fsm_rand_reset | 1.586m | 10.598ms | 10 | 10 | 100.00 | ||
| V2 | hartsel_warl | rv_dm_hartsel_warl | 0.970s | 148.063us | 1 | 1 | 100.00 |
| V2 | stress_all | rv_dm_stress_all | 1.940h | 10.000s | 3 | 50 | 6.00 |
| V2 | alert_test | rv_dm_alert_test | 1.290s | 142.979us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_dm_tl_errors | 4.510s | 596.680us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_dm_tl_errors | 4.510s | 596.680us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_dm_csr_aliasing | 52.710s | 4.370ms | 5 | 5 | 100.00 |
| rv_dm_csr_hw_reset | 2.100s | 557.681us | 5 | 5 | 100.00 | ||
| rv_dm_csr_rw | 2.380s | 351.059us | 20 | 20 | 100.00 | ||
| rv_dm_same_csr_outstanding | 7.180s | 856.922us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_dm_csr_aliasing | 52.710s | 4.370ms | 5 | 5 | 100.00 |
| rv_dm_csr_hw_reset | 2.100s | 557.681us | 5 | 5 | 100.00 | ||
| rv_dm_csr_rw | 2.380s | 351.059us | 20 | 20 | 100.00 | ||
| rv_dm_same_csr_outstanding | 7.180s | 856.922us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 117 | 251 | 46.61 | |||
| V2S | tl_intg_err | rv_dm_sec_cm | 2.760s | 1.542ms | 5 | 5 | 100.00 |
| rv_dm_tl_intg_err | 20.570s | 5.690ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_dm_tl_intg_err | 20.570s | 5.690ms | 20 | 20 | 100.00 |
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | rv_dm_sba_debug_disabled | 3.300s | 1.536ms | 2 | 2 | 100.00 |
| rv_dm_debug_disabled | 1.130s | 34.657us | 2 | 2 | 100.00 | ||
| V2S | sec_cm_lc_hw_debug_clr_intersig_mubi | sec_cm_lc_hw_debug_clr_intersig_mubi | 0 | 0 | -- | ||
| V2S | sec_cm_lc_dft_en_intersig_mubi | rv_dm_sba_debug_disabled | 3.300s | 1.536ms | 2 | 2 | 100.00 |
| rv_dm_debug_disabled | 1.130s | 34.657us | 2 | 2 | 100.00 | ||
| V2S | sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | rv_dm_smoke | 5.450s | 4.458ms | 2 | 2 | 100.00 |
| V2S | sec_cm_dm_en_ctrl_lc_gated | rv_dm_buffered_enable | 2.290s | 450.088us | 7 | 10 | 70.00 |
| V2S | sec_cm_sba_tl_lc_gate_fsm_sparse | rv_dm_sparse_lc_gate_fsm | 1.250s | 318.478us | 4 | 4 | 100.00 |
| V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | rv_dm_sparse_lc_gate_fsm | 1.250s | 318.478us | 4 | 4 | 100.00 |
| V2S | sec_cm_exec_ctrl_mubi | rv_dm_buffered_enable | 2.290s | 450.088us | 7 | 10 | 70.00 |
| V2S | TOTAL | 38 | 41 | 92.68 | |||
| V3 | stress_all_with_rand_reset | rv_dm_stress_all_with_rand_reset | 33.780s | 6.197ms | 1 | 10 | 10.00 |
| V3 | TOTAL | 1 | 10 | 10.00 | |||
| Unmapped tests | rv_dm_scanmode | 12.235m | 300.000ms | 0 | 1 | 0.00 | |
| TOTAL | 334 | 483 | 69.15 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 0 | 0.00 |
| V1 | 27 | 27 | 26 | 96.30 |
| V2 | 19 | 19 | 12 | 63.16 |
| V2S | 6 | 5 | 4 | 66.67 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 75.22 | 89.95 | 77.62 | 65.52 | 42.11 | 75.74 | 96.24 | 79.36 |
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 82 failures:
Test rv_dm_sba_tl_access has 20 failures.
0.rv_dm_sba_tl_access.35550637998749695217870463601009053057586447782575741282524806809348174151805
Line 90, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/0.rv_dm_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_dm_sba_tl_access.72934143113493157605532098461832411687986500793523621528072565548194550236948
Line 90, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/1.rv_dm_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 18 more failures.
Test rv_dm_delayed_resp_sba_tl_access has 20 failures.
0.rv_dm_delayed_resp_sba_tl_access.13254052707980686780593956863789163760704637556465814136522057292169679936549
Line 90, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/0.rv_dm_delayed_resp_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_dm_delayed_resp_sba_tl_access.9404333958303000095572486934205243286529328043761435189671749729778168697462
Line 90, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/1.rv_dm_delayed_resp_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 18 more failures.
Test rv_dm_bad_sba_tl_access has 20 failures.
0.rv_dm_bad_sba_tl_access.79244501220308602564255081974454558372257293273961718553639599865294518781786
Line 90, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/0.rv_dm_bad_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_dm_bad_sba_tl_access.84409934074828565111468941805545009075847823714745095136017684945585723695289
Line 90, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/1.rv_dm_bad_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 18 more failures.
Test rv_dm_autoincr_sba_tl_access has 20 failures.
0.rv_dm_autoincr_sba_tl_access.47770052367968176498857107973373273162935880815626681720391544447039825411612
Line 90, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/0.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_dm_autoincr_sba_tl_access.81420079114487887965180323663155602379784897782499849966806095624170302841716
Line 90, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/1.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 18 more failures.
Test rv_dm_scanmode has 1 failures.
0.rv_dm_scanmode.73094265538165584645606954886757074498081397685778706630759973218965308515558
Line 81, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/0.rv_dm_scanmode/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more tests.
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failedgmv(jtag_dmi_ral.dmstatus.anyhalted) == 'b (* [] vs * [])` has 19 failures:
Test rv_dm_mem_tl_access_resuming has 2 failures.
0.rv_dm_mem_tl_access_resuming.45377517854397500687909064572203678599974694538276004183035367826346150465046
Line 81, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/0.rv_dm_mem_tl_access_resuming/latest/run.log
UVM_ERROR @ 108649028 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 108649028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_dm_mem_tl_access_resuming.70180736743042243923200455565795648974301536696339025908865287861063154859740
Line 81, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/1.rv_dm_mem_tl_access_resuming/latest/run.log
UVM_ERROR @ 256166162 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 256166162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all_with_rand_reset has 4 failures.
0.rv_dm_stress_all_with_rand_reset.21353269448374686685494429350009609447633842211752301976674117748593548471990
Line 95, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1478441911 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1478441911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.rv_dm_stress_all_with_rand_reset.107952882470219409013208089437105095158839178838383609989685379990029583300190
Line 84, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 216864680 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 216864680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Test rv_dm_stress_all has 13 failures.
13.rv_dm_stress_all.109308607878099798820711716956744946629273439523676956406806286231641914140381
Line 84, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/13.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 2142114557 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 2142114557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
14.rv_dm_stress_all.107469615171288184246177229679890220364212463977389150949035444870451503651011
Line 82, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/14.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 163303424 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 163303424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 11 more failures.
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failedgmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (* [] vs * [])` has 18 failures:
0.rv_dm_hart_unavail.77624600335271988199815303620436077052886337551487069642132213981953914834863
Line 81, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/0.rv_dm_hart_unavail/latest/run.log
UVM_ERROR @ 265668771 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 265668771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_dm_hart_unavail.46576598011462698078091274475409286551834675795204154257774382002275307246996
Line 81, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/1.rv_dm_hart_unavail/latest/run.log
UVM_ERROR @ 121988315 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 121988315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
0.rv_dm_stress_all.36673202618079625993302864092963040824194302614437794564345675179661227114232
Line 84, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/0.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 3925168057 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 3925168057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.rv_dm_stress_all.14052008416526784224286212878080308159330386995437089427680697454210876480147
Line 84, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/2.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 1559767400 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1559767400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 10 more failures.
9.rv_dm_stress_all_with_rand_reset.63557584462471994444024494270082527138487249313427026326627141540682523602443
Line 101, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/9.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 489616376 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 489616376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*]) has 17 failures:
Test rv_dm_jtag_dmi_debug_disabled has 2 failures.
0.rv_dm_jtag_dmi_debug_disabled.107666443892558575910446169579130490040516571335253343045376416053837961352063
Line 81, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/0.rv_dm_jtag_dmi_debug_disabled/latest/run.log
UVM_ERROR @ 123249221 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (1867166347 [0x6f4ab28b] vs 0 [0x0])
UVM_INFO @ 123249221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_dm_jtag_dmi_debug_disabled.76613030341339694658802808012403296442839467872657504547000671706007248615311
Line 81, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/1.rv_dm_jtag_dmi_debug_disabled/latest/run.log
UVM_ERROR @ 406544263 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (2188778152 [0x82761aa8] vs 0 [0x0])
UVM_INFO @ 406544263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all_with_rand_reset has 1 failures.
1.rv_dm_stress_all_with_rand_reset.101892996750220870511759028779402524180240898777303753091263511243660353074996
Line 84, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 209505550 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (445138921 [0x1a8847e9] vs 0 [0x0])
UVM_INFO @ 209505550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all has 14 failures.
4.rv_dm_stress_all.22475298175949033526400831206987181191591588018397489182191276340482191899317
Line 82, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/4.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 543441083 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (2263698987 [0x86ed4e2b] vs 0 [0x0])
UVM_INFO @ 543441083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.rv_dm_stress_all.13237163242092463862184376977925017812266154905615592302588678277008579094428
Line 82, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/5.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 90768576 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (676032984 [0x284b71d8] vs 0 [0x0])
UVM_INFO @ 90768576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 12 more failures.
Job timed out after * minutes has 7 failures:
1.rv_dm_stress_all.84417842846051743933782698392970655016724538692447244821083449378003071574126
Log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/1.rv_dm_stress_all/latest/run.log
Job timed out after 180 minutes
3.rv_dm_stress_all.15282285776118258038190681646026577307448869999644784041136296901240291847826
Log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/3.rv_dm_stress_all/latest/run.log
Job timed out after 180 minutes
... and 5 more failures.
UVM_ERROR (rv_dm_buffered_enable_vseq.sv:164) [rv_dm_buffered_enable_vseq] Check failed saw_a_valid == tgt_copy == Sba (* [*] vs * [*]) has 3 failures:
1.rv_dm_buffered_enable.9057450912687419370303574351316119076185441695130111929706329991034230561607
Line 90, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/1.rv_dm_buffered_enable/latest/run.log
UVM_ERROR @ 613304918 ps: (rv_dm_buffered_enable_vseq.sv:164) [uvm_test_top.env.virtual_sequencer.rv_dm_buffered_enable_vseq] Check failed saw_a_valid == tgt_copy == Sba (0 [0x0] vs 1 [0x1])
UVM_INFO @ 613304918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.rv_dm_buffered_enable.3573392658149500861395478089068791644160785507395328134013787968799410358362
Line 91, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/5.rv_dm_buffered_enable/latest/run.log
UVM_ERROR @ 450088369 ps: (rv_dm_buffered_enable_vseq.sv:164) [uvm_test_top.env.virtual_sequencer.rv_dm_buffered_enable_vseq] Check failed saw_a_valid == tgt_copy == Sba (0 [0x0] vs 1 [0x1])
UVM_INFO @ 450088369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (cip_base_vseq.sv:1171) [rv_dm_common_vseq] Check failed (vseq_done) has 3 failures:
5.rv_dm_stress_all_with_rand_reset.24770634259233452342048526627878667753795347073361290286806928818634677532098
Line 105, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/5.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 1570708347 ps: (cip_base_vseq.sv:1171) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (vseq_done)
UVM_INFO @ 1570708347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.rv_dm_stress_all_with_rand_reset.109394445993055024259290919688476313680887430759472750952046503439627757618347
Line 119, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/6.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 3321938226 ps: (cip_base_vseq.sv:1171) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (vseq_done)
UVM_INFO @ 3321938226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.