RV_DM/USE_JTAG_INTERFACE Simulation Results

Saturday July 04 2026 15:22:18 UTC

GitHub Revision: f2bc21ca1e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	4.210s	2.802ms	2	2	100.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	2.240s	718.280us	5	5	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	2.460s	719.042us	20	20	100.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	21.430s	18.024ms	5	5	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	3.550s	1.308ms	5	5	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	14.150s	8.090ms	5	5	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	15.620s	9.924ms	20	20	100.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	1.497m	49.486ms	20	20	100.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	2.943m	105.547ms	5	5	100.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	1.010s	464.239us	2	2	100.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	1.050s	148.010us	2	2	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	1.180s	175.156us	2	2	100.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	2.030s	781.175us	2	2	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	1.790s	375.096us	2	2	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	1.710s	478.559us	2	2	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	0.990s	92.529us	2	2	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	2.660s	1.327ms	8	8	100.00
V1	progbuf_busy	rv_dm_cmderr_busy	1.010s	464.239us	2	2	100.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	0.970s	144.478us	2	2	100.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	1.960s	635.458us	2	2	100.00
V1	progbuf_exception	rv_dm_cmderr_exception	1.180s	175.156us	2	2	100.00
V1	rom_read_access	rv_dm_rom_read_access	1.080s	103.016us	2	2	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	1.870s	262.439us	5	5	100.00
V1	csr_rw	rv_dm_csr_rw	2.390s	1.056ms	20	20	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	53.740s	30.496ms	5	5	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	52.510s	8.623ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	3.760s	253.490us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	52.510s	8.623ms	5	5	100.00
		rv_dm_csr_rw	2.390s	1.056ms	20	20	100.00
V1	mem_walk	rv_dm_mem_walk	1.090s	137.989us	5	5	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	1.030s	94.067us	5	5	100.00
V1		TOTAL			180	180	100.00
V2	idcode	rv_dm_smoke	4.210s	2.802ms	2	2	100.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	1.830s	779.688us	2	2	100.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	1.590s	288.507us	2	2	100.00
V2	jtag_dmi_failed_op	rv_dm_dmi_failed_op	2.330s	585.077us	2	2	100.00
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	1.870s	1.294ms	2	2	100.00
V2	sba	rv_dm_sba_tl_access	12.344m	300.000ms	0	20	0.00
		rv_dm_delayed_resp_sba_tl_access	12.553m	300.000ms	0	20	0.00
V2	bad_sba	rv_dm_bad_sba_tl_access	14.202m	300.000ms	0	20	0.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	14.102m	300.000ms	0	20	0.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	1.110s	586.878us	2	2	100.00
V2	sba_debug_disabled	rv_dm_sba_debug_disabled	4.710s	4.541ms	2	2	100.00
V2	ndmreset_req	rv_dm_ndmreset_req	1.030s	168.067us	2	2	100.00
V2	hart_unavail	rv_dm_hart_unavail	1.140s	264.377us	5	5	100.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	3.670s	8.785ms	1	1	100.00
		rv_dm_tap_fsm_rand_reset	1.249m	8.450ms	10	10	100.00
V2	hartsel_warl	rv_dm_hartsel_warl	1.260s	279.563us	1	1	100.00
V2	stress_all	rv_dm_stress_all	20.450s	10.740ms	50	50	100.00
V2	alert_test	rv_dm_alert_test	1.150s	119.674us	50	50	100.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	5.550s	881.748us	20	20	100.00
V2	tl_d_illegal_access	rv_dm_tl_errors	5.550s	881.748us	20	20	100.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	52.510s	8.623ms	5	5	100.00
		rv_dm_csr_hw_reset	1.870s	262.439us	5	5	100.00
		rv_dm_csr_rw	2.390s	1.056ms	20	20	100.00
		rv_dm_same_csr_outstanding	5.750s	319.955us	20	20	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	52.510s	8.623ms	5	5	100.00
		rv_dm_csr_hw_reset	1.870s	262.439us	5	5	100.00
		rv_dm_csr_rw	2.390s	1.056ms	20	20	100.00
		rv_dm_same_csr_outstanding	5.750s	319.955us	20	20	100.00
V2		TOTAL			171	251	68.13
V2S	tl_intg_err	rv_dm_sec_cm	4.660s	1.475ms	5	5	100.00
		rv_dm_tl_intg_err	17.240s	1.851ms	19	20	95.00
V2S	sec_cm_bus_integrity	rv_dm_tl_intg_err	17.240s	1.851ms	19	20	95.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	rv_dm_sba_debug_disabled	4.710s	4.541ms	2	2	100.00
		rv_dm_debug_disabled	1.110s	59.752us	1	2	50.00
V2S	sec_cm_lc_hw_debug_clr_intersig_mubi	sec_cm_lc_hw_debug_clr_intersig_mubi			0	0	--
V2S	sec_cm_lc_dft_en_intersig_mubi	rv_dm_sba_debug_disabled	4.710s	4.541ms	2	2	100.00
		rv_dm_debug_disabled	1.110s	59.752us	1	2	50.00
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	rv_dm_smoke	4.210s	2.802ms	2	2	100.00
V2S	sec_cm_dm_en_ctrl_lc_gated	rv_dm_buffered_enable	1.920s	520.612us	10	10	100.00
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	1.110s	46.901us	4	4	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	1.110s	46.901us	4	4	100.00
V2S	sec_cm_exec_ctrl_mubi	rv_dm_buffered_enable	1.920s	520.612us	10	10	100.00
V2S		TOTAL			39	41	95.12
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	1.256m	7.704ms	10	10	100.00
V3		TOTAL			10	10	100.00
	Unmapped tests	rv_dm_scanmode	0.700s	47.283us	1	1	100.00
		TOTAL			401	483	83.02

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	27	27	27	100.00
V2	19	19	15	78.95
V2S	6	5	3	50.00
V3	1	1	1	100.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
79.41	95.54	89.24	70.51	85.37	88.38	95.39	31.48

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 80 failures:

  • Test rv_dm_sba_tl_access has 20 failures.

    • 0.rv_dm_sba_tl_access.8060701633133415179688348592412098917157609560184639484854811756718866047788
      Line 90, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_jtag_interface-sim-vcs/0.rv_dm_sba_tl_access/latest/run.log

        UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.rv_dm_sba_tl_access.36325545705004546079556307733439796460874472481617493808980217138628806794923
      Line 90, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_jtag_interface-sim-vcs/1.rv_dm_sba_tl_access/latest/run.log

        UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 18 more failures.

  • Test rv_dm_delayed_resp_sba_tl_access has 20 failures.

    • 0.rv_dm_delayed_resp_sba_tl_access.65518419931881971221322678876009607237574622480823435634983899412599458013461
      Line 90, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_jtag_interface-sim-vcs/0.rv_dm_delayed_resp_sba_tl_access/latest/run.log

        UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.rv_dm_delayed_resp_sba_tl_access.10619657728750339221815647537852491229630736246036040629129912663773090161086
      Line 90, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_jtag_interface-sim-vcs/1.rv_dm_delayed_resp_sba_tl_access/latest/run.log

        UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 18 more failures.

  • Test rv_dm_bad_sba_tl_access has 20 failures.

    • 0.rv_dm_bad_sba_tl_access.35736357918204088221973756030605814780188032744962149908658829097464818295787
      Line 90, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_jtag_interface-sim-vcs/0.rv_dm_bad_sba_tl_access/latest/run.log

        UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.rv_dm_bad_sba_tl_access.95261316533395510264140085182341311702386525863680688973202635387587733929441
      Line 90, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_jtag_interface-sim-vcs/1.rv_dm_bad_sba_tl_access/latest/run.log

        UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 18 more failures.

  • Test rv_dm_autoincr_sba_tl_access has 20 failures.

    • 0.rv_dm_autoincr_sba_tl_access.7948829035268472116080361420992996241279331536127570722089627938932259602541
      Line 90, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_jtag_interface-sim-vcs/0.rv_dm_autoincr_sba_tl_access/latest/run.log

        UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.rv_dm_autoincr_sba_tl_access.106162162649336170975562557844896474473676095672871074130161599757040564458689
      Line 90, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_jtag_interface-sim-vcs/1.rv_dm_autoincr_sba_tl_access/latest/run.log

        UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 18 more failures.

• UVM_ERROR (rv_dm_debug_disabled_vseq.sv:33) [rv_dm_debug_disabled_vseq] Check failed (rvalue == expected_output) has 1 failures:

  • Test rv_dm_debug_disabled has 1 failures.

    • 0.rv_dm_debug_disabled.14159142135535185175900265996761657361725462781407815245421600985173178052750
      Line 84, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_jtag_interface-sim-vcs/0.rv_dm_debug_disabled/latest/run.log

        UVM_ERROR @  59752458 ps: (rv_dm_debug_disabled_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.rv_dm_debug_disabled_vseq] Check failed (rvalue == expected_output)
        UVM_INFO @  59752458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1023) virtual_sequencer [rv_dm_common_vseq] expect alert:fatal_fault to fire has 1 failures:

  • Test rv_dm_tl_intg_err has 1 failures.

    • 12.rv_dm_tl_intg_err.78001167278446520417724416688136305498437789601911360376302114965517008977850
      Line 186, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_jtag_interface-sim-vcs/12.rv_dm_tl_intg_err/latest/run.log

        UVM_ERROR @ 615122818 ps: (cip_base_vseq.sv:1023) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] expect alert:fatal_fault to fire
        UVM_INFO @ 615122818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---