f2bc21ca1e| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 2.960s | 1.632ms | 20 | 20 | 100.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.850s | 21.355us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.830s | 13.256us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 3.140s | 368.629us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 1.010s | 118.134us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.470s | 30.956us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.830s | 13.256us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 1.010s | 118.134us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 75 | 75 | 100.00 | |||
| V2 | random_reset | rv_timer_random_reset | 10.770s | 18.382ms | 1 | 20 | 5.00 |
| V2 | disabled | rv_timer_disabled | 3.970s | 2.131ms | 20 | 20 | 100.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 13.398m | 1.041s | 10 | 10 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 13.398m | 1.041s | 10 | 10 | 100.00 |
| V2 | stress | rv_timer_stress_all | 6.880s | 6.380ms | 20 | 20 | 100.00 |
| V2 | alert_test | rv_timer_alert_test | 0.820s | 14.949us | 50 | 50 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.820s | 76.073us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 2.690s | 621.922us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 2.690s | 621.922us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.850s | 21.355us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.830s | 13.256us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 1.010s | 118.134us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 1.000s | 149.727us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.850s | 21.355us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.830s | 13.256us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 1.010s | 118.134us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 1.000s | 149.727us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 191 | 210 | 90.95 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 1.110s | 347.312us | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 1.570s | 133.516us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.570s | 133.516us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | min_value | rv_timer_min | 1.180s | 234.123us | 2 | 10 | 20.00 |
| V3 | max_value | rv_timer_max | 0.880s | 206.191us | 0 | 10 | 0.00 |
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 51.270s | 30.116ms | 15 | 20 | 75.00 |
| V3 | TOTAL | 17 | 40 | 42.50 | |||
| TOTAL | 308 | 350 | 88.00 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 8 | 8 | 7 | 87.50 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 3 | 3 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 95.72 | 100.00 | 100.00 | 78.66 | -- | 100.00 | 96.82 | 98.82 |
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 27 failures:
0.rv_timer_min.59173423741453090220927194354958254258249864175271717427877505618314642929989
Line 77, in log /home/runner/_work/pavona/pavona/scratch/main/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log
UVM_FATAL @ 167122294 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x7040a904) == 0x1
UVM_INFO @ 167122294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.rv_timer_min.40066496085074280164903941354431816670180121392397392817200758610865639942149
Line 79, in log /home/runner/_work/pavona/pavona/scratch/main/rv_timer-sim-vcs/2.rv_timer_min/latest/run.log
UVM_FATAL @ 229904633 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x5e787d04) == 0x1
UVM_INFO @ 229904633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
0.rv_timer_random_reset.39709643513293322488681557401375764051610634949934514508979593979185587262361
Line 78, in log /home/runner/_work/pavona/pavona/scratch/main/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log
UVM_FATAL @ 176047891 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x7a629704) == 0x1
UVM_INFO @ 176047891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_timer_random_reset.16989088736106680731434945050218591094881056139940300309373517179679125186711
Line 77, in log /home/runner/_work/pavona/pavona/scratch/main/rv_timer-sim-vcs/1.rv_timer_random_reset/latest/run.log
UVM_FATAL @ 1942090254 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x87605904) == 0x1
UVM_INFO @ 1942090254 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 17 more failures.
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 10 failures:
0.rv_timer_max.33318702027411599280062911141109568968439470905752399556431705056729689686864
Line 77, in log /home/runner/_work/pavona/pavona/scratch/main/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log
UVM_ERROR @ 712194448 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 712194448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_timer_max.63936800064641469004839973800583010799586796077392869585031226571768600894502
Line 77, in log /home/runner/_work/pavona/pavona/scratch/main/rv_timer-sim-vcs/1.rv_timer_max/latest/run.log
UVM_ERROR @ 164861196 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 164861196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:
5.rv_timer_stress_all_with_rand_reset.89868731696486168006569511794881862873180995547470535817890884549629596228224
Line 352, in log /home/runner/_work/pavona/pavona/scratch/main/rv_timer-sim-vcs/5.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3564241306 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 3564241306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.rv_timer_stress_all_with_rand_reset.94087615702572741604429006677983716082682643235081340183935618637005351518069
Line 280, in log /home/runner/_work/pavona/pavona/scratch/main/rv_timer-sim-vcs/7.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2706047841 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 2706047841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (cip_base_vseq.sv:1171) [rv_timer_common_vseq] Check failed (vseq_done) has 2 failures:
0.rv_timer_stress_all_with_rand_reset.74590028697244255996433024040516810062167970939130564153876995260616839646562
Line 170, in log /home/runner/_work/pavona/pavona/scratch/main/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 460390667 ps: (cip_base_vseq.sv:1171) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
UVM_INFO @ 460390667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_timer_stress_all_with_rand_reset.14507668892563729724912470951325656384515538021296370842369909592456002905594
Line 94, in log /home/runner/_work/pavona/pavona/scratch/main/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 1399517398 ps: (cip_base_vseq.sv:1171) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
UVM_INFO @ 1399517398 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---