f2bc21ca1e| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | soc_dbg_ctrl_smoke | 0.750s | 2.216us | 0 | 1 | 0.00 |
| V1 | feature1 | feature1 | 0 | 0 | -- | ||
| V1 | csr_hw_reset | soc_dbg_ctrl_csr_hw_reset | 0.850s | 27.763us | 3 | 3 | 100.00 |
| V1 | csr_rw | soc_dbg_ctrl_csr_rw | 0.860s | 21.910us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | soc_dbg_ctrl_csr_bit_bash | 2.480s | 441.299us | 3 | 3 | 100.00 |
| V1 | csr_aliasing | soc_dbg_ctrl_csr_aliasing | 0.930s | 71.854us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | soc_dbg_ctrl_csr_mem_rw_with_rand_reset | 1.780s | 100.127us | 3 | 3 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | soc_dbg_ctrl_csr_rw | 0.860s | 21.910us | 20 | 20 | 100.00 |
| soc_dbg_ctrl_csr_aliasing | 0.930s | 71.854us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 34 | 35 | 97.14 | |||
| V2 | intr_test | soc_dbg_ctrl_intr_test | 0 | 0 | -- | ||
| V2 | tl_d_oob_addr_access | soc_dbg_ctrl_tl_errors | 2.050s | 30.611us | 3 | 3 | 100.00 |
| V2 | tl_d_illegal_access | soc_dbg_ctrl_tl_errors | 2.050s | 30.611us | 3 | 3 | 100.00 |
| V2 | tl_d_outstanding_access | soc_dbg_ctrl_csr_hw_reset | 0.850s | 27.763us | 3 | 3 | 100.00 |
| soc_dbg_ctrl_csr_rw | 0.860s | 21.910us | 20 | 20 | 100.00 | ||
| soc_dbg_ctrl_csr_aliasing | 0.930s | 71.854us | 5 | 5 | 100.00 | ||
| soc_dbg_ctrl_same_csr_outstanding | 0.940s | 48.279us | 3 | 3 | 100.00 | ||
| V2 | tl_d_partial_access | soc_dbg_ctrl_csr_hw_reset | 0.850s | 27.763us | 3 | 3 | 100.00 |
| soc_dbg_ctrl_csr_rw | 0.860s | 21.910us | 20 | 20 | 100.00 | ||
| soc_dbg_ctrl_csr_aliasing | 0.930s | 71.854us | 5 | 5 | 100.00 | ||
| soc_dbg_ctrl_same_csr_outstanding | 0.940s | 48.279us | 3 | 3 | 100.00 | ||
| V2 | TOTAL | 6 | 6 | 100.00 | |||
| V2S | tl_intg_err | soc_dbg_ctrl_tl_intg_err | 1.430s | 102.426us | 6 | 6 | 100.00 |
| soc_dbg_ctrl_sec_cm | 0 | 0 | -- | ||||
| V2S | TOTAL | 6 | 6 | 100.00 | |||
| V3 | TOTAL | 0 | 0 | -- | |||
| Unmapped tests | soc_dbg_ctrl_stress_all_with_rand_reset | 0.740s | 1.873us | 0 | 1 | 0.00 | |
| soc_dbg_ctrl_stress_all | 0.700s | 0 | 1 | 0.00 | |||
| soc_dbg_ctrl_alert_test | 0.840s | 38.867us | 3 | 3 | 100.00 | ||
| TOTAL | 49 | 52 | 94.23 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 3 | 3 | 1 | 33.33 |
| V1 | 7 | 6 | 5 | 71.43 |
| V2 | 3 | 2 | 2 | 66.67 |
| V2S | 2 | 1 | 1 | 50.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 74.48 | 86.75 | 88.18 | 85.81 | 0.00 | 81.70 | 96.16 | 82.74 |
UVM_WARNING [BDTYP] Cannot create an object of type 'soc_dbg_ctrl_stress_all_vseq' because it is not registered with the factory. has 2 failures:
Test soc_dbg_ctrl_stress_all_with_rand_reset has 1 failures.
0.soc_dbg_ctrl_stress_all_with_rand_reset.58111893964399686020887991088489659551799870372443831739494970828558908622630
Line 78, in log /home/runner/_work/pavona/pavona/scratch/main/soc_dbg_ctrl-sim-vcs/0.soc_dbg_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_WARNING @ 1872827 ps: [BDTYP] Cannot create an object of type 'soc_dbg_ctrl_stress_all_vseq' because it is not registered with the factory.
UVM_INFO @ 1872827 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
Test soc_dbg_ctrl_stress_all has 1 failures.
0.soc_dbg_ctrl_stress_all.26567225290198400779844695531553923079547740027601698726560341764703037227405
Line 78, in log /home/runner/_work/pavona/pavona/scratch/main/soc_dbg_ctrl-sim-vcs/0.soc_dbg_ctrl_stress_all/latest/run.log
UVM_WARNING @ 0 ps: [BDTYP] Cannot create an object of type 'soc_dbg_ctrl_stress_all_vseq' because it is not registered with the factory.
UVM_INFO @ 0 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
UVM_ERROR (soc_dbg_ctrl_smoke_vseq.sv:19) virtual_sequencer [soc_dbg_ctrl_smoke_vseq] FIXME has 1 failures:
0.soc_dbg_ctrl_smoke.77357173655822286446466049981874358437583357596968236217587214720216089168866
Line 88, in log /home/runner/_work/pavona/pavona/scratch/main/soc_dbg_ctrl-sim-vcs/0.soc_dbg_ctrl_smoke/latest/run.log
UVM_ERROR @ 2216263 ps: (soc_dbg_ctrl_smoke_vseq.sv:19) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.soc_dbg_ctrl_smoke_vseq] FIXME
UVM_INFO @ 2216263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---