SPI_DEVICE/1R1W Simulation Results

Saturday July 04 2026 15:22:18 UTC

GitHub Revision: f2bc21ca1e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	8.486m	253.205ms	8	8	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.190s	49.969us	3	3	100.00
V1	csr_rw	spi_device_csr_rw	2.450s	229.549us	3	3	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	23.250s	6.926ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	10.790s	223.983us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.320s	320.025us	3	3	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.450s	229.549us	3	3	100.00
		spi_device_csr_aliasing	10.790s	223.983us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.880s	20.039us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.740s	81.114us	5	5	100.00
V1		TOTAL			37	37	100.00
V2	csb_read	spi_device_csb_read	0.950s	62.760us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.930s	3.668us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.920s	4.300us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	3.070s	1.210ms	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	3.070s	1.210ms	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	4.090s	2.292ms	1	1	100.00
		spi_device_tpm_sts_read	1.050s	42.233us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	18.220s	4.542ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	2.980s	243.125us	1	1	100.00
		spi_device_flash_all	7.269m	78.867ms	5	5	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	19.040s	26.253ms	4	4	100.00
		spi_device_flash_all	7.269m	78.867ms	5	5	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	19.040s	26.253ms	4	4	100.00
		spi_device_flash_all	7.269m	78.867ms	5	5	100.00
V2	cmd_info_slots	spi_device_flash_all	7.269m	78.867ms	5	5	100.00
V2	cmd_read_status	spi_device_intercept	4.280s	1.226ms	1	1	100.00
		spi_device_flash_all	7.269m	78.867ms	5	5	100.00
V2	cmd_read_jedec	spi_device_intercept	4.280s	1.226ms	1	1	100.00
		spi_device_flash_all	7.269m	78.867ms	5	5	100.00
V2	cmd_read_sfdp	spi_device_intercept	4.280s	1.226ms	1	1	100.00
		spi_device_flash_all	7.269m	78.867ms	5	5	100.00
V2	cmd_fast_read	spi_device_intercept	4.280s	1.226ms	1	1	100.00
		spi_device_flash_all	7.269m	78.867ms	5	5	100.00
V2	cmd_read_pipeline	spi_device_intercept	4.280s	1.226ms	1	1	100.00
		spi_device_flash_all	7.269m	78.867ms	5	5	100.00
V2	flash_cmd_upload	spi_device_upload	6.290s	449.605us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	2.022m	15.824ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.022m	15.824ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.022m	15.824ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	22.100s	1.999ms	7	7	100.00
		spi_device_read_buffer_direct	9.800s	1.372ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.022m	15.824ms	1	1	100.00
		spi_device_flash_all	7.269m	78.867ms	5	5	100.00
V2	quad_spi	spi_device_flash_all	7.269m	78.867ms	5	5	100.00
V2	dual_spi	spi_device_flash_all	7.269m	78.867ms	5	5	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	2.870s	334.999us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	2.870s	334.999us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	8.486m	253.205ms	8	8	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	8.407m	284.085ms	5	5	100.00
V2	stress_all	spi_device_stress_all	15.792m	509.509ms	18	18	100.00
V2	alert_test	spi_device_alert_test	0.910s	31.200us	3	3	100.00
V2	intr_test	spi_device_intr_test	0.980s	16.478us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.550s	197.937us	5	5	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.550s	197.937us	5	5	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.190s	49.969us	3	3	100.00
		spi_device_csr_rw	2.450s	229.549us	3	3	100.00
		spi_device_csr_aliasing	10.790s	223.983us	5	5	100.00
		spi_device_same_csr_outstanding	3.040s	198.917us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.190s	49.969us	3	3	100.00
		spi_device_csr_rw	2.450s	229.549us	3	3	100.00
		spi_device_csr_aliasing	10.790s	223.983us	5	5	100.00
		spi_device_same_csr_outstanding	3.040s	198.917us	20	20	100.00
V2		TOTAL			128	149	85.91
V2S	tl_intg_err	spi_device_sec_cm	1.360s	85.863us	3	3	100.00
		spi_device_tl_intg_err	14.910s	1.537ms	6	6	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	14.910s	1.537ms	6	6	100.00
V2S		TOTAL			9	9	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	6.142m	52.902ms	9	9	100.00
		TOTAL			183	204	89.71

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	20	90.91
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.31	98.90	96.53	83.01	89.36	98.32	94.76	99.26

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 20 failures:
  • Test spi_device_mem_parity has 20 failures.

    • 0.spi_device_mem_parity.21025921869784838666938256653547174380544686023444428388092582585710866056281
      Line 78, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   1051233 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[13])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1051233 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   1051233 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[909])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

    • 1.spi_device_mem_parity.55734363313863512471623148630573578060617183846992589116712100536182927013896
      Line 78, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   3287466 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[62])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   3287466 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   3287466 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[958])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

    • ... and 18 more failures.

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:
  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.54590783355599798371245702627895444584804032983533532073753809459634435556375
      Line 78, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   1827849 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xe2ec99 [111000101110110010011001] vs 0x0 [0])
        UVM_ERROR @   1838849 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xbc52b0 [101111000101001010110000] vs 0x0 [0])
        UVM_ERROR @   1843849 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xfcb9f8 [111111001011100111111000] vs 0x0 [0])
        UVM_ERROR @   1853849 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xf5fe47 [111101011111111001000111] vs 0x0 [0])
        UVM_ERROR @   1936849 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xfac144 [111110101100000101000100] vs 0x0 [0])