SPI_DEVICE/2P Simulation Results

Saturday July 04 2026 15:22:18 UTC

GitHub Revision: f2bc21ca1e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_device_flash_and_tpm 5.464m 210.488ms 19 19 100.00
V1 csr_hw_reset spi_device_csr_hw_reset 1.500s 44.795us 3 3 100.00
V1 csr_rw spi_device_csr_rw 1.900s 122.115us 3 3 100.00
V1 csr_bit_bash spi_device_csr_bit_bash 21.790s 6.666ms 5 5 100.00
V1 csr_aliasing spi_device_csr_aliasing 15.510s 3.728ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_device_csr_mem_rw_with_rand_reset 3.400s 220.553us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_device_csr_rw 1.900s 122.115us 3 3 100.00
spi_device_csr_aliasing 15.510s 3.728ms 5 5 100.00
V1 mem_walk spi_device_mem_walk 0.940s 11.967us 5 5 100.00
V1 mem_partial_access spi_device_mem_partial_access 1.870s 253.710us 5 5 100.00
V1 TOTAL 65 65 100.00
V2 csb_read spi_device_csb_read 0.590s 34.233us 1 1 100.00
V2 mem_parity spi_device_mem_parity 1.200s 83.478us 3 3 100.00
V2 mem_cfg spi_device_ram_cfg 0.940s 29.235us 3 3 100.00
V2 tpm_read spi_device_tpm_rw 0.830s 43.099us 1 1 100.00
V2 tpm_write spi_device_tpm_rw 0.830s 43.099us 1 1 100.00
V2 tpm_hw_reg spi_device_tpm_read_hw_reg 1.470s 763.575us 1 1 100.00
spi_device_tpm_sts_read 0.810s 76.641us 1 1 100.00
V2 tpm_fully_random_case spi_device_tpm_all 28.810s 31.987ms 4 4 100.00
V2 pass_cmd_filtering spi_device_pass_cmd_filtering 18.410s 7.256ms 1 1 100.00
spi_device_flash_all 4.802m 59.497ms 7 7 100.00
V2 pass_addr_translation spi_device_pass_addr_payload_swap 10.940s 6.455ms 1 1 100.00
spi_device_flash_all 4.802m 59.497ms 7 7 100.00
V2 pass_payload_translation spi_device_pass_addr_payload_swap 10.940s 6.455ms 1 1 100.00
spi_device_flash_all 4.802m 59.497ms 7 7 100.00
V2 cmd_info_slots spi_device_flash_all 4.802m 59.497ms 7 7 100.00
V2 cmd_read_status spi_device_intercept 8.230s 4.700ms 1 1 100.00
spi_device_flash_all 4.802m 59.497ms 7 7 100.00
V2 cmd_read_jedec spi_device_intercept 8.230s 4.700ms 1 1 100.00
spi_device_flash_all 4.802m 59.497ms 7 7 100.00
V2 cmd_read_sfdp spi_device_intercept 8.230s 4.700ms 1 1 100.00
spi_device_flash_all 4.802m 59.497ms 7 7 100.00
V2 cmd_fast_read spi_device_intercept 8.230s 4.700ms 1 1 100.00
spi_device_flash_all 4.802m 59.497ms 7 7 100.00
V2 cmd_read_pipeline spi_device_intercept 8.230s 4.700ms 1 1 100.00
spi_device_flash_all 4.802m 59.497ms 7 7 100.00
V2 flash_cmd_upload spi_device_upload 2.130s 468.444us 1 1 100.00
V2 mailbox_command spi_device_mailbox 19.850s 1.888ms 3 3 100.00
V2 mailbox_cross_outside_command spi_device_mailbox 19.850s 1.888ms 3 3 100.00
V2 mailbox_cross_inside_command spi_device_mailbox 19.850s 1.888ms 3 3 100.00
V2 cmd_read_buffer spi_device_flash_mode 31.040s 22.851ms 7 7 100.00
spi_device_read_buffer_direct 7.320s 658.449us 1 1 100.00
V2 cmd_dummy_cycle spi_device_mailbox 19.850s 1.888ms 3 3 100.00
spi_device_flash_all 4.802m 59.497ms 7 7 100.00
V2 quad_spi spi_device_flash_all 4.802m 59.497ms 7 7 100.00
V2 dual_spi spi_device_flash_all 4.802m 59.497ms 7 7 100.00
V2 4b_3b_feature spi_device_cfg_cmd 4.780s 336.862us 1 1 100.00
V2 write_enable_disable spi_device_cfg_cmd 4.780s 336.862us 1 1 100.00
V2 TPM_with_flash_or_passthrough_mode spi_device_flash_and_tpm 5.464m 210.488ms 19 19 100.00
V2 tpm_and_flash_trans_with_min_inactive_time spi_device_flash_and_tpm_min_idle 4.190m 41.433ms 7 7 100.00
V2 stress_all spi_device_stress_all 8.059m 947.442ms 11 11 100.00
V2 alert_test spi_device_alert_test 0.940s 21.649us 3 3 100.00
V2 intr_test spi_device_intr_test 0.990s 40.186us 3 3 100.00
V2 tl_d_oob_addr_access spi_device_tl_errors 5.010s 82.356us 4 4 100.00
V2 tl_d_illegal_access spi_device_tl_errors 5.010s 82.356us 4 4 100.00
V2 tl_d_outstanding_access spi_device_csr_hw_reset 1.500s 44.795us 3 3 100.00
spi_device_csr_rw 1.900s 122.115us 3 3 100.00
spi_device_csr_aliasing 15.510s 3.728ms 5 5 100.00
spi_device_same_csr_outstanding 3.880s 472.267us 20 20 100.00
V2 tl_d_partial_access spi_device_csr_hw_reset 1.500s 44.795us 3 3 100.00
spi_device_csr_rw 1.900s 122.115us 3 3 100.00
spi_device_csr_aliasing 15.510s 3.728ms 5 5 100.00
spi_device_same_csr_outstanding 3.880s 472.267us 20 20 100.00
V2 TOTAL 85 85 100.00
V2S tl_intg_err spi_device_sec_cm 1.620s 961.875us 3 3 100.00
spi_device_tl_intg_err 19.130s 915.108us 6 6 100.00
V2S sec_cm_bus_integrity spi_device_tl_intg_err 19.130s 915.108us 6 6 100.00
V2S TOTAL 9 9 100.00
V3 stress_all_with_rand_reset spi_device_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
Unmapped tests spi_device_flash_mode_ignore_cmds 5.336m 163.550ms 6 6 100.00
TOTAL 165 165 100.00

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 1 100.00
V1 8 8 8 100.00
V2 22 22 22 100.00
V2S 2 2 2 100.00
V3 1 0 0 0.00

Coverage Results

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
94.99 98.96 96.63 87.57 89.36 98.40 94.74 99.26