SPI_HOST Simulation Results

Saturday July 04 2026 15:22:18 UTC

GitHub Revision: f2bc21ca1e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	2.729m	23.231ms	50	50	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	0.880s	59.475us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	0.900s	17.671us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	2.330s	163.650us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	0.980s	25.139us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	1.300s	46.851us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	0.900s	17.671us	20	20	100.00
		spi_host_csr_aliasing	0.980s	25.139us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	0.850s	17.568us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	0.930s	144.164us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	performance	spi_host_performance	2.370s	264.712us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	5.100s	370.123us	50	50	100.00
		spi_host_error_cmd	0.920s	20.265us	50	50	100.00
		spi_host_event	8.709m	48.613ms	50	50	100.00
V2	clock_rate	spi_host_speed	5.630s	590.825us	50	50	100.00
V2	speed	spi_host_speed	5.630s	590.825us	50	50	100.00
V2	chip_select_timing	spi_host_speed	5.630s	590.825us	50	50	100.00
V2	sw_reset	spi_host_sw_reset	14.800m	21.437ms	47	50	94.00
V2	passthrough_mode	spi_host_passthrough_mode	0.910s	148.109us	50	50	100.00
V2	cpol_cpha	spi_host_speed	5.630s	590.825us	50	50	100.00
V2	full_cycle	spi_host_speed	5.630s	590.825us	50	50	100.00
V2	duplex	spi_host_smoke	2.729m	23.231ms	50	50	100.00
V2	tx_rx_only	spi_host_smoke	2.729m	23.231ms	50	50	100.00
V2	stress_all	spi_host_stress_all	9.768m	1.000s	49	50	98.00
V2	spien	spi_host_spien	2.996m	41.575ms	50	50	100.00
V2	stall	spi_host_status_stall	30.233m	1.000s	47	50	94.00
V2	Idlecsbactive	spi_host_idlecsbactive	37.470s	2.482ms	50	50	100.00
V2	data_fifo_status	spi_host_overflow_underflow	5.100s	370.123us	50	50	100.00
V2	alert_test	spi_host_alert_test	0.890s	32.725us	50	50	100.00
V2	intr_test	spi_host_intr_test	0.860s	17.649us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	2.330s	672.983us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	2.330s	672.983us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	0.880s	59.475us	5	5	100.00
		spi_host_csr_rw	0.900s	17.671us	20	20	100.00
		spi_host_csr_aliasing	0.980s	25.139us	5	5	100.00
		spi_host_same_csr_outstanding	1.030s	34.517us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	0.880s	59.475us	5	5	100.00
		spi_host_csr_rw	0.900s	17.671us	20	20	100.00
		spi_host_csr_aliasing	0.980s	25.139us	5	5	100.00
		spi_host_same_csr_outstanding	1.030s	34.517us	20	20	100.00
V2		TOTAL			683	690	98.99
V2S	tl_intg_err	spi_host_tl_intg_err	1.570s	109.180us	20	20	100.00
		spi_host_sec_cm	1.300s	872.666us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	1.570s	109.180us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	winbond	winbond			0	0	--
V3	stress_all_with_rand_reset	spi_host_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_host_upper_range_clkdiv	59.425m	100.006ms	3	10	30.00
		TOTAL			826	840	98.33

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	8	8	8	100.00
V2	15	15	12	80.00
V2S	2	2	2	100.00
V3	2	0	0	0.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
89.16	97.51	90.13	74.60	88.24	92.16	95.64	85.80

Failure Buckets

• UVM_FATAL (spi_host_base_vseq.sv:233) virtual_sequencer [spi_host_env_pkg::\spi_host_base_vseq::stoppable_timeout ()] timeout = *ns spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=* has 4 failures:

  • Test spi_host_upper_range_clkdiv has 4 failures.

    • 0.spi_host_upper_range_clkdiv.18080156598392733597511583990860306933855046466721019184045406213808831265014
      Line 132, in log /home/runner/_work/pavona/pavona/scratch/main/spi_host-sim-vcs/0.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 100007248884 ps: (spi_host_base_vseq.sv:233) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::\spi_host_base_vseq::stoppable_timeout ()] timeout = 100000000ns spi_host_reg_block.status.rxempty (addr=0x67063114, Comparison=CompareOpEq, exp_data=0x0, call_count=6
        UVM_INFO @ 100007248884 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.spi_host_upper_range_clkdiv.78353725244740714001257490220293363827844549450134292001470890423512305447793
      Line 139, in log /home/runner/_work/pavona/pavona/scratch/main/spi_host-sim-vcs/1.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 100005510166 ps: (spi_host_base_vseq.sv:233) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::\spi_host_base_vseq::stoppable_timeout ()] timeout = 100000000ns spi_host_reg_block.status.rxempty (addr=0x5bb0d994, Comparison=CompareOpEq, exp_data=0x0, call_count=6
        UVM_INFO @ 100005510166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 2 more failures.

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:

  • Test spi_host_upper_range_clkdiv has 1 failures.

    • 5.spi_host_upper_range_clkdiv.107541444343805497853096491405873286954839395051110488409342282654497124838269
      Line 184, in log /home/runner/_work/pavona/pavona/scratch/main/spi_host-sim-vcs/5.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test spi_host_status_stall has 2 failures.

    • 9.spi_host_status_stall.62984562812163969830906347773580023370859960935259163920956868359268769331420
      Line 16215, in log /home/runner/_work/pavona/pavona/scratch/main/spi_host-sim-vcs/9.spi_host_status_stall/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 28.spi_host_status_stall.14731336193606559771234871620242758758346706023984850193771932175058143572787
      Line 1403, in log /home/runner/_work/pavona/pavona/scratch/main/spi_host-sim-vcs/28.spi_host_status_stall/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test spi_host_stress_all has 1 failures.

    • 40.spi_host_stress_all.91410231256965704629568155187154714148447444775559188988919884144032908625596
      Line 271, in log /home/runner/_work/pavona/pavona/scratch/main/spi_host-sim-vcs/40.spi_host_stress_all/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (spi_host_base_vseq.sv:227) virtual_sequencer [spi_host_env_pkg::\spi_host_base_vseq::stoppable_timeout .unnamed$$_*] Event has already been triggered with stop=* has 3 failures:

  • Test spi_host_sw_reset has 3 failures.

    • 13.spi_host_sw_reset.69079506991511797761169614457489208472319814479802518793886878289103845334639
      Line 175, in log /home/runner/_work/pavona/pavona/scratch/main/spi_host-sim-vcs/13.spi_host_sw_reset/latest/run.log

        UVM_FATAL @  41263983 ps: (spi_host_base_vseq.sv:227) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::\spi_host_base_vseq::stoppable_timeout .unnamed$$_0] Event has already been triggered with stop=1
        UVM_INFO @  41263983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 17.spi_host_sw_reset.37374947831006771137514908717419153392548777826878135660196733091621207511634
      Line 320, in log /home/runner/_work/pavona/pavona/scratch/main/spi_host-sim-vcs/17.spi_host_sw_reset/latest/run.log

        UVM_FATAL @ 2495933904 ps: (spi_host_base_vseq.sv:227) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::\spi_host_base_vseq::stoppable_timeout .unnamed$$_0] Event has already been triggered with stop=1
        UVM_INFO @ 2495933904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_FATAL (spi_host_base_vseq.sv:233) virtual_sequencer [spi_host_env_pkg::\spi_host_base_vseq::stoppable_timeout ()] timeout = *ns spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=* has 2 failures:

  • Test spi_host_upper_range_clkdiv has 2 failures.

    • 2.spi_host_upper_range_clkdiv.71134687140323698675355096933003519262036263178523043113776085282063962998205
      Line 142, in log /home/runner/_work/pavona/pavona/scratch/main/spi_host-sim-vcs/2.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 100013223958 ps: (spi_host_base_vseq.sv:233) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::\spi_host_base_vseq::stoppable_timeout ()] timeout = 100000000ns spi_host_reg_block.status.active (addr=0x5b911214, Comparison=CompareOpEq, exp_data=0x0, call_count=14
        UVM_INFO @ 100013223958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 9.spi_host_upper_range_clkdiv.65689345133753698196580595346970897952086904948539399594821041968116247517702
      Line 182, in log /home/runner/_work/pavona/pavona/scratch/main/spi_host-sim-vcs/9.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 183744449010 ps: (spi_host_base_vseq.sv:233) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::\spi_host_base_vseq::stoppable_timeout ()] timeout = 100000000ns spi_host_reg_block.status.active (addr=0x90b7f7d4, Comparison=CompareOpEq, exp_data=0x0, call_count=21
        UVM_INFO @ 183744449010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(!$changed(signal2check_i[*]))' has 1 failures:

  • Test spi_host_status_stall has 1 failures.

    • 12.spi_host_status_stall.94225482943124373966425845811710836504139761016969956133724287145912244102661
      Line 3772, in log /home/runner/_work/pavona/pavona/scratch/main/spi_host-sim-vcs/12.spi_host_status_stall/latest/run.log

            Offending '(!$changed(signal2check_i[1]))'
        UVM_ERROR @ 26663979844 ps: [NEGEDGE_SAME_VALUE_CHECK_P] tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1].NEGEDGE_SAME_VALUE_CHECK_P: [i=1] - ASSERTION FAILED pos_value (0x0) != neg_value (0x0) - time=26663980000 ps
        UVM_INFO @ 26663979844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---