SRAM_CTRL/EXEC_64KB Simulation Results

Saturday July 04 2026 15:22:18 UTC

GitHub Revision: f2bc21ca1e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	16.040s	1.588ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.960s	70.364us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.900s	16.703us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.450s	67.623us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.970s	22.231us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.000s	195.218us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.900s	16.703us	20	20	100.00
		sram_ctrl_csr_aliasing	0.970s	22.231us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	53.840s	2.643ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.134m	1.279ms	1	1	100.00
V1		TOTAL			58	58	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	4.653m	817.078us	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.138m	3.241ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	16.717m	360.715ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	25.701m	119.757ms	3	3	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	9.520s	2.309ms	1	1	100.00
V2	executable	sram_ctrl_executable	27.355m	45.241ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	17.670s	2.442ms	1	1	100.00
		sram_ctrl_partial_access_b2b	5.378m	24.585ms	4	4	100.00
V2	max_throughput	sram_ctrl_max_throughput	17.480s	1.285ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	21.670s	391.099us	1	1	100.00
		sram_ctrl_throughput_w_readback	2.021m	2.270ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	4.909m	14.772ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.350s	963.835us	3	3	100.00
V2	stress_all	sram_ctrl_stress_all	1.368h	449.163ms	4	4	100.00
V2	alert_test	sram_ctrl_alert_test	0.850s	16.654us	3	3	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.650s	586.666us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.650s	586.666us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.960s	70.364us	5	5	100.00
		sram_ctrl_csr_rw	0.900s	16.703us	20	20	100.00
		sram_ctrl_csr_aliasing	0.970s	22.231us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.060s	94.623us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.960s	70.364us	5	5	100.00
		sram_ctrl_csr_rw	0.900s	16.703us	20	20	100.00
		sram_ctrl_csr_aliasing	0.970s	22.231us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.060s	94.623us	20	20	100.00
V2		TOTAL			67	67	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	19.680s	3.809ms	3	3	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	4.100s	1.543ms	3	3	100.00
		sram_ctrl_tl_intg_err	3.140s	1.826ms	8	8	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	4.100s	1.543ms	3	3	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.140s	1.826ms	8	8	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	4.909m	14.772ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	4.909m	14.772ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.900s	16.703us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	27.355m	45.241ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	27.355m	45.241ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	27.355m	45.241ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	9.520s	2.309ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	3.720s	364.179us	4	4	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	19.680s	3.809ms	3	3	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	3.560s	1.385ms	4	4	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	16.040s	1.588ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	16.040s	1.588ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	27.355m	45.241ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	4.100s	1.543ms	3	3	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	9.520s	2.309ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	4.100s	1.543ms	3	3	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	4.100s	1.543ms	3	3	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	16.040s	1.588ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	4.100s	1.543ms	3	3	100.00
V2S		TOTAL			22	22	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	2.617m	3.396ms	6	6	100.00
V3		TOTAL			6	6	100.00
		TOTAL			153	153	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	17	17	17	100.00
V2S	5	5	5	100.00
V3	1	1	1	100.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.37	98.75	96.46	85.96	80.00	97.32	96.38	98.70