SRAM_CTRL/MAIN Simulation Results

Saturday July 04 2026 15:22:18 UTC

GitHub Revision: f2bc21ca1e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.200s	691.437us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.960s	44.203us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.920s	11.333us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.990s	937.814us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.920s	18.821us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	4.090s	1.487ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.920s	11.333us	20	20	100.00
		sram_ctrl_csr_aliasing	0.920s	18.821us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	2.632m	57.409ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.083m	18.263ms	1	1	100.00
V1		TOTAL			58	58	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	9.265m	122.688ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.330m	26.128ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	12.387m	378.251ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	18.363m	75.569ms	3	3	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	45.950s	47.439ms	3	3	100.00
V2	executable	sram_ctrl_executable	18.242m	117.252ms	3	3	100.00
V2	partial_access	sram_ctrl_partial_access	3.340s	1.480ms	1	1	100.00
		sram_ctrl_partial_access_b2b	6.931m	18.751ms	3	3	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.087m	1.488ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	20.930s	2.954ms	1	1	100.00
		sram_ctrl_throughput_w_readback	2.306m	1.560ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	8.821m	11.895ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	3.460s	691.886us	3	3	100.00
V2	stress_all	sram_ctrl_stress_all	1.489h	266.225ms	4	4	100.00
V2	alert_test	sram_ctrl_alert_test	0.930s	32.437us	3	3	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.840s	409.508us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.840s	409.508us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.960s	44.203us	5	5	100.00
		sram_ctrl_csr_rw	0.920s	11.333us	20	20	100.00
		sram_ctrl_csr_aliasing	0.920s	18.821us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.930s	149.286us	3	3	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.960s	44.203us	5	5	100.00
		sram_ctrl_csr_rw	0.920s	11.333us	20	20	100.00
		sram_ctrl_csr_aliasing	0.920s	18.821us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.930s	149.286us	3	3	100.00
V2		TOTAL			53	53	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	50.620s	7.611ms	4	4	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	4.570s	5.195ms	3	3	100.00
		sram_ctrl_tl_intg_err	2.490s	495.798us	8	8	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	4.570s	5.195ms	3	3	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.490s	495.798us	8	8	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	8.821m	11.895ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	8.821m	11.895ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.920s	11.333us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	18.242m	117.252ms	3	3	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	18.242m	117.252ms	3	3	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	18.242m	117.252ms	3	3	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	45.950s	47.439ms	3	3	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	6.090s	2.773ms	3	3	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	50.620s	7.611ms	4	4	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	5.220s	2.868ms	4	5	80.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.200s	691.437us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.200s	691.437us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	18.242m	117.252ms	3	3	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	4.570s	5.195ms	3	3	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	45.950s	47.439ms	3	3	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	4.570s	5.195ms	3	3	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	4.570s	5.195ms	3	3	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.200s	691.437us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	4.570s	5.195ms	3	3	100.00
V2S		TOTAL			22	23	95.65
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	1.154m	5.017ms	6	6	100.00
V3		TOTAL			6	6	100.00
		TOTAL			139	140	99.29

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	17	17	17	100.00
V2S	5	5	4	80.00
V3	1	1	1	100.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.13	98.75	96.34	91.21	80.00	97.32	96.38	98.89

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 1 failures:
  • Test sram_ctrl_readback_err has 1 failures.

    • 4.sram_ctrl_readback_err.98688425817557244019288372482766493988725398504712038987887073588979349591622
      Line 102, in log /home/runner/_work/pavona/pavona/scratch/main/sram_ctrl_main-sim-vcs/4.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 658872391 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x4e) != exp (0x79)
        UVM_INFO @ 658872391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---