SRAM_CTRL/RET Simulation Results

Saturday July 04 2026 15:22:18 UTC

GitHub Revision: f2bc21ca1e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.140s	209.818us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.970s	16.658us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.980s	14.432us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.720s	177.362us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.010s	62.169us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.080s	260.390us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.980s	14.432us	20	20	100.00
		sram_ctrl_csr_aliasing	1.010s	62.169us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	8.530s	7.230ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.830s	390.743us	1	1	100.00
V1		TOTAL			57	58	98.28
V2	multiple_keys	sram_ctrl_multiple_keys	15.558m	92.552ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.191m	7.566ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	10.340s	2.824ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	10.071m	9.546ms	3	3	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	6.610s	1.573ms	1	1	100.00
V2	executable	sram_ctrl_executable	16.981m	6.591ms	3	3	100.00
V2	partial_access	sram_ctrl_partial_access	1.440s	350.315us	1	1	100.00
		sram_ctrl_partial_access_b2b	4.862m	31.597ms	3	3	100.00
V2	max_throughput	sram_ctrl_max_throughput	3.560s	211.650us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	1.786m	853.808us	1	1	100.00
		sram_ctrl_throughput_w_readback	11.290s	201.828us	1	1	100.00
V2	regwen	sram_ctrl_regwen	14.260m	16.468ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.000s	84.863us	3	3	100.00
V2	stress_all	sram_ctrl_stress_all	40.668m	47.120ms	4	4	100.00
V2	alert_test	sram_ctrl_alert_test	0.860s	12.155us	3	3	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.390s	235.580us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.390s	235.580us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.970s	16.658us	5	5	100.00
		sram_ctrl_csr_rw	0.980s	14.432us	20	20	100.00
		sram_ctrl_csr_aliasing	1.010s	62.169us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.050s	122.168us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.970s	16.658us	5	5	100.00
		sram_ctrl_csr_rw	0.980s	14.432us	20	20	100.00
		sram_ctrl_csr_aliasing	1.010s	62.169us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.050s	122.168us	20	20	100.00
V2		TOTAL			68	68	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.020s	2.237ms	5	5	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	4.230s	1.490ms	5	5	100.00
		sram_ctrl_tl_intg_err	2.320s	2.059ms	6	6	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	4.230s	1.490ms	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.320s	2.059ms	6	6	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	14.260m	16.468ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	14.260m	16.468ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.980s	14.432us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	16.981m	6.591ms	3	3	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	16.981m	6.591ms	3	3	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	16.981m	6.591ms	3	3	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	6.610s	1.573ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.260s	495.662us	5	5	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.020s	2.237ms	5	5	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.060s	27.135us	2	3	66.67
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.140s	209.818us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.140s	209.818us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	16.981m	6.591ms	3	3	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	4.230s	1.490ms	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	6.610s	1.573ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	4.230s	1.490ms	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	4.230s	1.490ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.140s	209.818us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	4.230s	1.490ms	5	5	100.00
V2S		TOTAL			23	24	95.83
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	4.169m	520.699us	4	4	100.00
V3		TOTAL			4	4	100.00
		TOTAL			152	154	98.70

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	17	17	17	100.00
V2S	5	5	4	80.00
V3	1	1	1	100.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.13	98.70	96.46	91.21	80.00	97.26	96.35	98.89

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 1 failures:

  • Test sram_ctrl_readback_err has 1 failures.

    • 2.sram_ctrl_readback_err.79957229494995310345708337105220762482179055158491513170243203259827487625969
      Line 102, in log /home/runner/_work/pavona/pavona/scratch/main/sram_ctrl_ret-sim-vcs/2.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @  27134631 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x5a) != exp (0x1)
        UVM_INFO @  27134631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status reset value: * has 1 failures:

  • Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 10.sram_ctrl_csr_mem_rw_with_rand_reset.95489593346257350870986886604924860806577209175939146096950881925181813223984
      Line 102, in log /home/runner/_work/pavona/pavona/scratch/main/sram_ctrl_ret-sim-vcs/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @  47102475 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (40 [0x28] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0
        UVM_INFO @  47102475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---