SYSRST_CTRL Simulation Results

Saturday July 04 2026 15:22:18 UTC

GitHub Revision: f2bc21ca1e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	3.660s	2.114ms	1	1	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	1.020s	2.497ms	1	1	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	6.880s	2.411ms	5	5	100.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	7.180s	2.537ms	5	5	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	8.000s	6.027ms	5	5	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	5.690s	2.036ms	20	20	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	1.898m	75.390ms	3	3	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	5.070s	2.815ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	4.900s	2.063ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	5.690s	2.036ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	5.070s	2.815ms	5	5	100.00
V1		TOTAL			65	65	100.00
V2	combo_detect	sysrst_ctrl_combo_detect	2.030m	67.155ms	5	5	100.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	5.152m	132.458ms	37	38	97.37
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	9.870s	3.621ms	4	4	100.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	10.990s	3.838ms	22	22	100.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	7.660s	2.511ms	3	3	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	1.120s	2.277ms	1	1	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	1.800s	3.156ms	1	1	100.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	1.550s	2.632ms	1	1	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	2.733m	1.368s	5	5	100.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	1.422m	38.545ms	9	9	100.00
V2	stress_all	sysrst_ctrl_stress_all	7.095m	653.927ms	24	24	100.00
V2	alert_test	sysrst_ctrl_alert_test	5.420s	2.010ms	3	3	100.00
V2	intr_test	sysrst_ctrl_intr_test	4.540s	2.013ms	50	50	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	6.360s	2.148ms	5	5	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	6.360s	2.148ms	5	5	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	8.000s	6.027ms	5	5	100.00
		sysrst_ctrl_csr_rw	5.690s	2.036ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	5.070s	2.815ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	9.310s	5.155ms	3	3	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	8.000s	6.027ms	5	5	100.00
		sysrst_ctrl_csr_rw	5.690s	2.036ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	5.070s	2.815ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	9.310s	5.155ms	3	3	100.00
V2		TOTAL			173	174	99.43
V2S	tl_intg_err	sysrst_ctrl_sec_cm	48.630s	22.005ms	3	3	100.00
		sysrst_ctrl_tl_intg_err	1.107m	42.407ms	3	3	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	1.107m	42.407ms	3	3	100.00
V2S		TOTAL			6	6	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	1.713m	1.197s	7	7	100.00
V3		TOTAL			7	7	100.00
		TOTAL			251	252	99.60

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	15	15	14	93.33
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.40	99.70	98.26	100.00	98.72	99.85	98.56	86.71

Failure Buckets

• UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(9) vs exp(4) +/-* has 1 failures:
  • Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

    • 34.sysrst_ctrl_combo_detect_with_pre_cond.77477452142315980689616807913028214637297088178640477599567898428375446168038
      Line 669, in log /home/runner/_work/pavona/pavona/scratch/main/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

        UVM_ERROR @ 24381065183 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(9) vs exp(4) +/-4
        UVM_INFO @ 34680931033 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x2c
        UVM_INFO @ 34681556033 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x18
        UVM_INFO @ 35508806033 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 2
        UVM_INFO @ 35521065183 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:399) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] combo_precondition_mask= 1d