UART Simulation Results

Saturday July 04 2026 15:22:18 UTC

GitHub Revision: f2bc21ca1e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	35.090s	11.095ms	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.880s	16.526us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.870s	17.357us	3	3	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.990s	226.212us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.960s	279.328us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.490s	207.266us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.870s	17.357us	3	3	100.00
		uart_csr_aliasing	0.960s	279.328us	5	5	100.00
V1		TOTAL			39	39	100.00
V2	base_random_seq	uart_tx_rx	2.079m	170.681ms	3	3	100.00
V2	parity	uart_smoke	35.090s	11.095ms	1	1	100.00
		uart_tx_rx	2.079m	170.681ms	3	3	100.00
V2	parity_error	uart_intr	2.954m	99.989ms	4	4	100.00
		uart_rx_parity_err	2.143m	263.952ms	3	3	100.00
V2	watermark	uart_tx_rx	2.079m	170.681ms	3	3	100.00
		uart_intr	2.954m	99.989ms	4	4	100.00
V2	fifo_full	uart_fifo_full	4.192m	155.240ms	9	9	100.00
V2	fifo_overflow	uart_fifo_overflow	2.161m	71.708ms	5	5	100.00
V2	fifo_reset	uart_fifo_reset	6.245m	251.247ms	55	55	100.00
V2	rx_frame_err	uart_intr	2.954m	99.989ms	4	4	100.00
V2	rx_break_err	uart_intr	2.954m	99.989ms	4	4	100.00
V2	rx_timeout	uart_intr	2.954m	99.989ms	4	4	100.00
V2	perf	uart_perf	6.962m	11.000ms	1	1	100.00
V2	sys_loopback	uart_loopback	23.030s	10.921ms	1	1	100.00
V2	line_loopback	uart_loopback	23.030s	10.921ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	2.910s	15.902ms	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	5.870s	3.457ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	3.020s	934.017us	4	4	100.00
V2	rx_oversample	uart_rx_oversample	16.570s	5.308ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	11.100m	97.141ms	3	3	100.00
V2	stress_all	uart_stress_all	17.659m	390.990ms	16	17	94.12
V2	alert_test	uart_alert_test	0.820s	13.515us	3	3	100.00
V2	intr_test	uart_intr_test	0.860s	15.132us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.330s	116.211us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.330s	116.211us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.880s	16.526us	5	5	100.00
		uart_csr_rw	0.870s	17.357us	3	3	100.00
		uart_csr_aliasing	0.960s	279.328us	5	5	100.00
		uart_same_csr_outstanding	0.990s	25.258us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.880s	16.526us	5	5	100.00
		uart_csr_rw	0.870s	17.357us	3	3	100.00
		uart_csr_aliasing	0.960s	279.328us	5	5	100.00
		uart_same_csr_outstanding	0.990s	25.258us	20	20	100.00
V2		TOTAL			199	201	99.00
V2S	tl_intg_err	uart_sec_cm	1.130s	214.416us	3	3	100.00
		uart_tl_intg_err	1.460s	76.914us	5	5	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.460s	76.914us	5	5	100.00
V2S		TOTAL			8	8	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	2.113m	5.406ms	9	9	100.00
V3		TOTAL			9	9	100.00
		TOTAL			255	257	99.22

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	16	88.89
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.35	99.48	98.25	91.55	--	98.14	97.12	99.59

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * has 1 failures:

  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.45577202685104631103218861869536632065242643573755294091954373862439145749125
      Line 76, in log /home/runner/_work/pavona/pavona/scratch/main/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @  27448753 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @  38073753 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 2056323753 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0
        UVM_ERROR @ 2056448753 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 2056573753 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
      

• UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 1 failures:

  • Test uart_stress_all has 1 failures.

    • 13.uart_stress_all.55759030504258409823756276504935379874448516515478438398239219427783082835220
      Line 84, in log /home/runner/_work/pavona/pavona/scratch/main/uart-sim-vcs/13.uart_stress_all/latest/run.log

        UVM_ERROR @ 8637361529 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0
        UVM_ERROR @ 8637371630 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 8637381731 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
        UVM_ERROR @ 8728401842 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 5,                                 clk_pulses: 0
        UVM_ERROR @ 8728411943 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty