AC_RANGE_CHECK/DRAGONFLY Simulation Results

Sunday August 02 2026 00:03:30 UTC

GitHub Revision: `0ff052588e`

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	ac_range_check_smoke	ac_range_check_smoke	17.650s	1.482m	5.197ms	20	20	100.00
V1	ac_range_check_smoke_racl	ac_range_check_smoke_racl	28.110s	1.601m	2.037ms	42	46	91.30
V1	csr_hw_reset	ac_range_check_csr_hw_reset	1.100s	1.049m	136.242us	5	5	100.00
V1	csr_rw	ac_range_check_csr_rw	1.140s	1.012m	52.543us	20	20	100.00
V1	csr_bit_bash	ac_range_check_csr_bit_bash	17.050s	1.233m	5.104ms	5	5	100.00
V1	csr_aliasing	ac_range_check_csr_aliasing	13.530s	1.179m	2.874ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	ac_range_check_csr_mem_rw_with_rand_reset	1.150s	35.675s	26.367us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	ac_range_check_csr_rw	1.140s	1.012m	52.543us	20	20	100.00
		ac_range_check_csr_aliasing	13.530s	1.179m	2.874ms	5	5	100.00
V1		TOTAL				117	121	96.69
V2	ac_range_check_lock_range	ac_range_check_lock_range	1.540s	1.198m	90.073us	20	20	100.00
V2	ac_range_bypass_enable	ac_range_check_bypass	13.730s	27.155s	1.944ms	1	1	100.00
V2	stress_all	ac_range_check_stress_all	2.179m	2.819m	12.850ms	80	84	95.24
V2	alert_test	ac_range_check_alert_test	0.560s	39.462s	41.057us	3	3	100.00
V2	intr_test	ac_range_check_intr_test	0.740s	1.049m	13.868us	4	4	100.00
V2	tl_d_oob_addr_access	ac_range_check_tl_errors	2.060s	1.196m	663.784us	20	20	100.00
V2	tl_d_illegal_access	ac_range_check_tl_errors	2.060s	1.196m	663.784us	20	20	100.00
V2	tl_d_outstanding_access	ac_range_check_csr_hw_reset	1.100s	1.049m	136.242us	5	5	100.00
		ac_range_check_csr_rw	1.140s	1.012m	52.543us	20	20	100.00
		ac_range_check_csr_aliasing	13.530s	1.179m	2.874ms	5	5	100.00
		ac_range_check_same_csr_outstanding	2.160s	35.857s	147.496us	3	3	100.00
V2	tl_d_partial_access	ac_range_check_csr_hw_reset	1.100s	1.049m	136.242us	5	5	100.00
		ac_range_check_csr_rw	1.140s	1.012m	52.543us	20	20	100.00
		ac_range_check_csr_aliasing	13.530s	1.179m	2.874ms	5	5	100.00
		ac_range_check_same_csr_outstanding	2.160s	35.857s	147.496us	3	3	100.00
V2		TOTAL				131	135	97.04
V2S	shadow_reg_update_error	ac_range_check_shadow_reg_errors	11.720s	1.275m	1.202ms	6	6	100.00
V2S	shadow_reg_read_clear_staged_value	ac_range_check_shadow_reg_errors	11.720s	1.275m	1.202ms	6	6	100.00
V2S	shadow_reg_storage_error	ac_range_check_shadow_reg_errors	11.720s	1.275m	1.202ms	6	6	100.00
V2S	shadowed_reset_glitch	ac_range_check_shadow_reg_errors	11.720s	1.275m	1.202ms	6	6	100.00
V2S	shadow_reg_update_error_with_csr_rw	ac_range_check_shadow_reg_errors_with_csr_rw	57.980s	2.054m	5.390ms	20	20	100.00
V2S	tl_intg_err	ac_range_check_sec_cm	0.640s	55.555s	12.759us	5	5	100.00
		ac_range_check_tl_intg_err	5.170s	1.245m	1.617ms	17	17	100.00
V2S		TOTAL				48	48	100.00
V3	stress_all_with_rand_reset	ac_range_check_stress_all_with_rand_reset	3.290m	3.923m	3.071ms	6	6	100.00
V3		TOTAL				6	6	100.00
	Unmapped tests	ac_range_check_smoke_high_threshold	18.260s	1.389m	23.010ms	15	15	100.00
		ac_range_check_rst_safe_smoke	6.168m	6.730m	100.029ms	14	16	87.50
		TOTAL				331	341	97.07

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	2	2	1	50.00
V1	7	7	6	85.71
V2	7	7	6	85.71
V2S	4	4	4	100.00
V3	1	1	1	100.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.90	99.87	98.40	83.44	--	99.55	97.75	84.35

Simulation Wall Clock Time

Target	Elapsed
build	00:07:13
run	30:46:43
cov_merge	30:47:37
cov_report	30:47:52
Total	30:47:52

Failure Buckets

UVM_ERROR (ac_range_check_scoreboard.sv:373) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: ac_range_check_reg_block.intr_state has 8 failures:

Test ac_range_check_rst_safe_smoke has 1 failures.

13.ac_range_check_rst_safe_smoke.35410847934311445357697840891742691195166122356074646001970325052277380772929
Line 4324, in log /home/runner/_work/pavona/pavona/scratch/main/ac_range_check_top_dragonfly-sim-vcs/13.ac_range_check_rst_safe_smoke/latest/run.log

  UVM_ERROR @ 418314794 ps: (ac_range_check_scoreboard.sv:373) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
  UVM_INFO @ 418314794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test ac_range_check_smoke_racl has 4 failures.

31.ac_range_check_smoke_racl.71611391349268024071865628864010280363158218179493796052706845091512702898342
Line 4393, in log /home/runner/_work/pavona/pavona/scratch/main/ac_range_check_top_dragonfly-sim-vcs/31.ac_range_check_smoke_racl/latest/run.log

  UVM_ERROR @ 39887801246 ps: (ac_range_check_scoreboard.sv:373) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
  UVM_INFO @ 39887801246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

32.ac_range_check_smoke_racl.49241502387139763398310413556233983445676111853919381449989220389199680664967
Line 4207, in log /home/runner/_work/pavona/pavona/scratch/main/ac_range_check_top_dragonfly-sim-vcs/32.ac_range_check_smoke_racl/latest/run.log

  UVM_ERROR @ 575403577 ps: (ac_range_check_scoreboard.sv:373) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
  UVM_INFO @ 575403577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test ac_range_check_stress_all has 3 failures.

68.ac_range_check_stress_all.10186383603442128755026556218251027392111854047555916875727303324091702321653
Line 8709, in log /home/runner/_work/pavona/pavona/scratch/main/ac_range_check_top_dragonfly-sim-vcs/68.ac_range_check_stress_all/latest/run.log

  UVM_ERROR @ 1075022184 ps: (ac_range_check_scoreboard.sv:373) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
  UVM_INFO @ 1075022184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

75.ac_range_check_stress_all.91020423947217043465078366799564290450431650243051434270865319230311631045995
Line 4796, in log /home/runner/_work/pavona/pavona/scratch/main/ac_range_check_top_dragonfly-sim-vcs/75.ac_range_check_stress_all/latest/run.log

  UVM_ERROR @ 4983017703 ps: (ac_range_check_scoreboard.sv:373) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
  UVM_INFO @ 4983017703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Offending '(pend_req[h2d.a_source].pend == *)' has 1 failures:

Test ac_range_check_rst_safe_smoke has 1 failures.

11.ac_range_check_rst_safe_smoke.69914805314475707964725653767206230295224325115860530980548593134269569838023
Line 4701, in log /home/runner/_work/pavona/pavona/scratch/main/ac_range_check_top_dragonfly-sim-vcs/11.ac_range_check_rst_safe_smoke/latest/run.log

      Offending '(pend_req[h2d.a_source].pend == 0)'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 284: tb.dut.tlul_assert_device.gen_device.gen_h2d.pendingReqPerSrc_M: started at 972495539ps failed at 972495539ps
      Offending '(pend_req[h2d.a_source].pend == 0)'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 284: tb.dut.tlul_assert_device.gen_device.gen_h2d.pendingReqPerSrc_M: started at 972537205ps failed at 972537205ps
      Offending '(pend_req[h2d.a_source].pend == 0)'

UVM_ERROR (ac_range_check_predictor.sv:163) [predict] Unable to get any item from tl_filt_d_chan_fifo. has 1 failures:
- Test ac_range_check_stress_all has 1 failures.
  - 69.ac_range_check_stress_all.40523555188695853178946604499559073635934782267979884763988285519274461378752
    Line 16274, in log /home/runner/_work/pavona/pavona/scratch/main/ac_range_check_top_dragonfly-sim-vcs/69.ac_range_check_stress_all/latest/run.log
```
  UVM_ERROR @ 100388156735 ps: (ac_range_check_predictor.sv:163) [uvm_test_top.env.scoreboard.predict] Unable to get any item from tl_filt_d_chan_fifo.
  UVM_INFO @ 100388156735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```