ACC/PQC Simulation Results

Sunday August 02 2026 00:03:30 UTC

GitHub Revision: 0ff052588e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Max Wall Clock Simulated Time Passing Total Pass Rate
V1 smoke acc_smoke 11.360s 3.200m 199.248us 4 4 100.00
V1 single_binary acc_single 20.370s 3.184m 191.518us 46 46 100.00
V1 csr_hw_reset acc_csr_hw_reset 1.910s 31.143s 25.950us 5 5 100.00
V1 csr_rw acc_csr_rw 1.510s 33.266s 33.217us 20 20 100.00
V1 csr_bit_bash acc_csr_bit_bash 3.130s 32.118s 108.664us 5 5 100.00
V1 csr_aliasing acc_csr_aliasing 1.950s 31.116s 26.839us 5 5 100.00
V1 csr_mem_rw_with_rand_reset acc_csr_mem_rw_with_rand_reset 3.620s 33.181s 32.717us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr acc_csr_rw 1.510s 33.266s 33.217us 20 20 100.00
acc_csr_aliasing 1.950s 31.116s 26.839us 5 5 100.00
V1 mem_walk acc_mem_walk 1.763m 2.065m 2.054ms 5 5 100.00
V1 mem_partial_access acc_mem_partial_access 1.162m 1.578m 8.292ms 5 5 100.00
V1 TOTAL 115 115 100.00
V2 reset_recovery acc_reset 28.620s 3.435m 430.367us 11 11 100.00
V2 multi_error acc_multi_err 27.060s 3.720m 230.918us 3 3 100.00
V2 back_to_back acc_multi 9.108m 10.447m 6.709ms 15 16 93.75
V2 stress_all acc_stress_all 2.849m 3.770m 2.248ms 21 22 95.45
V2 lc_escalation acc_escalate 18.820s 3.150m 647.407us 19 19 100.00
V2 zero_state_err_urnd acc_zero_state_err_urnd 2.800s 2.952m 65.668us 4 4 100.00
V2 sw_errs_fatal_chk acc_sw_errs_fatal_chk 10.470s 2.666m 107.295us 10 10 100.00
V2 alert_test acc_alert_test 1.330s 16.073s 26.134us 3 3 100.00
V2 intr_test acc_intr_test 1.580s 37.110s 97.488us 3 3 100.00
V2 tl_d_oob_addr_access acc_tl_errors 4.180s 32.102s 432.447us 20 20 100.00
V2 tl_d_illegal_access acc_tl_errors 4.180s 32.102s 432.447us 20 20 100.00
V2 tl_d_outstanding_access acc_csr_hw_reset 1.910s 31.143s 25.950us 5 5 100.00
acc_csr_rw 1.510s 33.266s 33.217us 20 20 100.00
acc_csr_aliasing 1.950s 31.116s 26.839us 5 5 100.00
acc_same_csr_outstanding 1.810s 27.232s 63.533us 20 20 100.00
V2 tl_d_partial_access acc_csr_hw_reset 1.910s 31.143s 25.950us 5 5 100.00
acc_csr_rw 1.510s 33.266s 33.217us 20 20 100.00
acc_csr_aliasing 1.950s 31.116s 26.839us 5 5 100.00
acc_same_csr_outstanding 1.810s 27.232s 63.533us 20 20 100.00
V2 TOTAL 129 131 98.47
V2S mem_integrity acc_imem_err 4.830s 3.019m 78.390us 5 5 100.00
acc_dmem_err 4.940s 3.069m 39.103us 4 4 100.00
V2S internal_integrity acc_alu_bignum_mod_err 21.070s 3.086m 878.952us 5 5 100.00
acc_controller_ispr_rdata_err 15.890s 3.133m 115.594us 10 10 100.00
acc_mac_bignum_acc_err 12.750s 3.002m 489.773us 9 10 90.00
acc_urnd_err 2.050s 13.900s 28.938us 3 3 100.00
V2S kmac_error acc_kmac_err 5.030s 3.052m 536.450us 6 8 75.00
V2S illegal_bus_access acc_illegal_mem_acc 3.270s 3.066m 102.327us 8 8 100.00
V2S acc_mem_gnt_acc_err acc_mem_gnt_acc_err 4.380s 19.095s 48.066us 4 5 80.00
V2S acc_non_sec_partial_wipe acc_partial_wipe 3.520s 22.163s 41.278us 8 9 88.89
V2S tl_intg_err acc_sec_cm 1.608m 2.047m 2.260ms 5 5 100.00
acc_tl_intg_err 16.130s 43.171s 566.321us 6 6 100.00
V2S passthru_mem_tl_intg_err acc_passthru_mem_tl_intg_err 41.700s 1.023m 872.446us 3 4 75.00
V2S prim_fsm_check acc_sec_cm 1.608m 2.047m 2.260ms 5 5 100.00
V2S prim_count_check acc_sec_cm 1.608m 2.047m 2.260ms 5 5 100.00
V2S sec_cm_mem_scramble acc_smoke 11.360s 3.200m 199.248us 4 4 100.00
V2S sec_cm_data_mem_integrity acc_dmem_err 4.940s 3.069m 39.103us 4 4 100.00
V2S sec_cm_instruction_mem_integrity acc_imem_err 4.830s 3.019m 78.390us 5 5 100.00
V2S sec_cm_bus_integrity acc_tl_intg_err 16.130s 43.171s 566.321us 6 6 100.00
V2S sec_cm_controller_fsm_global_esc acc_escalate 18.820s 3.150m 647.407us 19 19 100.00
V2S sec_cm_controller_fsm_local_esc acc_imem_err 4.830s 3.019m 78.390us 5 5 100.00
acc_dmem_err 4.940s 3.069m 39.103us 4 4 100.00
acc_zero_state_err_urnd 2.800s 2.952m 65.668us 4 4 100.00
acc_illegal_mem_acc 3.270s 3.066m 102.327us 8 8 100.00
acc_sec_cm 1.608m 2.047m 2.260ms 5 5 100.00
V2S sec_cm_controller_fsm_sparse acc_sec_cm 1.608m 2.047m 2.260ms 5 5 100.00
V2S sec_cm_scramble_key_sideload acc_single 20.370s 3.184m 191.518us 46 46 100.00
V2S sec_cm_scramble_ctrl_fsm_local_esc acc_imem_err 4.830s 3.019m 78.390us 5 5 100.00
acc_dmem_err 4.940s 3.069m 39.103us 4 4 100.00
acc_zero_state_err_urnd 2.800s 2.952m 65.668us 4 4 100.00
acc_illegal_mem_acc 3.270s 3.066m 102.327us 8 8 100.00
acc_sec_cm 1.608m 2.047m 2.260ms 5 5 100.00
V2S sec_cm_scramble_ctrl_fsm_sparse acc_sec_cm 1.608m 2.047m 2.260ms 5 5 100.00
V2S sec_cm_start_stop_ctrl_fsm_global_esc acc_escalate 18.820s 3.150m 647.407us 19 19 100.00
V2S sec_cm_start_stop_ctrl_fsm_local_esc acc_imem_err 4.830s 3.019m 78.390us 5 5 100.00
acc_dmem_err 4.940s 3.069m 39.103us 4 4 100.00
acc_zero_state_err_urnd 2.800s 2.952m 65.668us 4 4 100.00
acc_illegal_mem_acc 3.270s 3.066m 102.327us 8 8 100.00
acc_sec_cm 1.608m 2.047m 2.260ms 5 5 100.00
V2S sec_cm_start_stop_ctrl_fsm_sparse acc_sec_cm 1.608m 2.047m 2.260ms 5 5 100.00
V2S sec_cm_data_reg_sw_sca acc_single 20.370s 3.184m 191.518us 46 46 100.00
V2S sec_cm_ctrl_redun acc_ctrl_redun 4.750s 23.218s 157.316us 14 14 100.00
V2S sec_cm_pc_ctrl_flow_redun acc_pc_ctrl_flow_redun 2.620s 1.901m 115.373us 3 3 100.00
V2S sec_cm_rnd_bus_consistency acc_rnd_sec_cm 1.617m 1.962m 13.630ms 6 6 100.00
V2S sec_cm_rnd_rng_digest acc_rnd_sec_cm 1.617m 1.962m 13.630ms 6 6 100.00
V2S sec_cm_rf_base_data_reg_sw_integrity acc_rf_base_intg_err 3.890s 2.985m 94.334us 8 9 88.89
V2S sec_cm_rf_base_data_reg_sw_glitch_detect acc_sec_cm 1.608m 2.047m 2.260ms 5 5 100.00
V2S sec_cm_stack_wr_ptr_ctr_redun acc_sec_cm 1.608m 2.047m 2.260ms 5 5 100.00
V2S sec_cm_rf_bignum_data_reg_sw_integrity acc_rf_bignum_intg_err 8.710s 3.116m 168.691us 15 15 100.00
V2S sec_cm_rf_bignum_data_reg_sw_glitch_detect acc_sec_cm 1.608m 2.047m 2.260ms 5 5 100.00
V2S sec_cm_loop_stack_ctr_redun acc_sec_cm 1.608m 2.047m 2.260ms 5 5 100.00
V2S sec_cm_loop_stack_addr_integrity acc_stack_addr_integ_chk 17.590s 29.986s 552.562us 5 7 71.43
V2S sec_cm_call_stack_addr_integrity acc_stack_addr_integ_chk 17.590s 29.986s 552.562us 5 7 71.43
V2S sec_cm_start_stop_ctrl_state_consistency acc_sec_wipe_err 3.010s 18.115s 15.806us 6 7 85.71
V2S sec_cm_data_mem_sec_wipe acc_single 20.370s 3.184m 191.518us 46 46 100.00
V2S sec_cm_instruction_mem_sec_wipe acc_single 20.370s 3.184m 191.518us 46 46 100.00
V2S sec_cm_data_reg_sw_sec_wipe acc_single 20.370s 3.184m 191.518us 46 46 100.00
V2S sec_cm_write_mem_integrity acc_multi 9.108m 10.447m 6.709ms 15 16 93.75
V2S sec_cm_ctrl_flow_count acc_single 20.370s 3.184m 191.518us 46 46 100.00
V2S sec_cm_ctrl_flow_sca acc_single 20.370s 3.184m 191.518us 46 46 100.00
V2S sec_cm_data_mem_sw_noaccess acc_sw_no_acc 12.740s 25.238s 80.858us 7 7 100.00
V2S sec_cm_key_sideload acc_single 20.370s 3.184m 191.518us 46 46 100.00
V2S sec_cm_tlul_fifo_ctr_redun acc_sec_cm 1.608m 2.047m 2.260ms 5 5 100.00
V2S TOTAL 140 150 93.33
V3 stress_all_with_rand_reset acc_stress_all_with_rand_reset 3.754m 4.457m 27.115ms 3 4 75.00
V3 TOTAL 3 4 75.00
TOTAL 387 400 96.75

Testplan Progress

Items Total Written Passing Progress
V1 9 9 9 100.00
V2 11 11 9 81.82
V2S 21 21 13 61.90
V3 1 1 0 0.00

Coverage Results

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
94.14 92.26 94.18 96.16 89.13 93.11 96.84 97.29

Simulation Wall Clock Time

Target Elapsed
build 00:07:13
run 30:46:43
cov_merge 30:47:37
cov_report 30:47:52
Total 30:47:52

Failure Buckets