ACC/STANDARD Simulation Results

Sunday August 02 2026 00:03:30 UTC

GitHub Revision: 0ff052588e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	smoke	acc_smoke	5.910s	20.082s	72.982us	3	3	100.00
V1	single_binary	acc_single	12.840s	20.090s	190.027us	18	18	100.00
V1	csr_hw_reset	acc_csr_hw_reset	1.640s	49.079s	22.811us	3	3	100.00
V1	csr_rw	acc_csr_rw	1.540s	53.080s	207.725us	20	20	100.00
V1	csr_bit_bash	acc_csr_bit_bash	3.710s	55.086s	539.483us	5	5	100.00
V1	csr_aliasing	acc_csr_aliasing	1.660s	53.089s	23.848us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	acc_csr_mem_rw_with_rand_reset	4.050s	51.087s	87.491us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	acc_csr_rw	1.540s	53.080s	207.725us	20	20	100.00
		acc_csr_aliasing	1.660s	53.089s	23.848us	5	5	100.00
V1	mem_walk	acc_mem_walk	1.466m	2.205m	4.052ms	5	5	100.00
V1	mem_partial_access	acc_mem_partial_access	56.700s	1.702m	9.486ms	5	5	100.00
V1		TOTAL				84	84	100.00
V2	reset_recovery	acc_reset	25.700s	36.147s	125.211us	8	8	100.00
V2	multi_error	acc_multi_err	27.750s	56.375s	257.798us	3	3	100.00
V2	back_to_back	acc_multi	1.426m	1.879m	869.058us	12	13	92.31
V2	stress_all	acc_stress_all	1.458m	1.985m	644.387us	24	25	96.00
V2	lc_escalation	acc_escalate	7.920s	15.071s	46.106us	15	16	93.75
V2	zero_state_err_urnd	acc_zero_state_err_urnd	3.090s	11.091s	72.679us	4	4	100.00
V2	sw_errs_fatal_chk	acc_sw_errs_fatal_chk	15.860s	24.131s	122.835us	8	8	100.00
V2	alert_test	acc_alert_test	1.630s	6.039s	26.383us	3	3	100.00
V2	intr_test	acc_intr_test	1.470s	1.201m	26.722us	50	50	100.00
V2	tl_d_oob_addr_access	acc_tl_errors	4.020s	1.352m	575.776us	20	20	100.00
V2	tl_d_illegal_access	acc_tl_errors	4.020s	1.352m	575.776us	20	20	100.00
V2	tl_d_outstanding_access	acc_csr_hw_reset	1.640s	49.079s	22.811us	3	3	100.00
		acc_csr_rw	1.540s	53.080s	207.725us	20	20	100.00
		acc_csr_aliasing	1.660s	53.089s	23.848us	5	5	100.00
		acc_same_csr_outstanding	1.610s	49.090s	200.523us	3	3	100.00
V2	tl_d_partial_access	acc_csr_hw_reset	1.640s	49.079s	22.811us	3	3	100.00
		acc_csr_rw	1.540s	53.080s	207.725us	20	20	100.00
		acc_csr_aliasing	1.660s	53.089s	23.848us	5	5	100.00
		acc_same_csr_outstanding	1.610s	49.090s	200.523us	3	3	100.00
V2		TOTAL				150	153	98.04
V2S	mem_integrity	acc_imem_err	5.470s	13.050s	54.346us	8	8	100.00
		acc_dmem_err	20.040s	29.143s	2.455ms	5	5	100.00
V2S	internal_integrity	acc_alu_bignum_mod_err	7.110s	15.136s	228.265us	8	8	100.00
		acc_controller_ispr_rdata_err	14.140s	22.226s	524.726us	10	10	100.00
		acc_mac_bignum_acc_err	9.320s	18.244s	153.628us	11	11	100.00
		acc_urnd_err	2.930s	10.064s	13.643us	4	4	100.00
V2S	kmac_error	acc_kmac_err				0	0	--
V2S	illegal_bus_access	acc_illegal_mem_acc	2.760s	10.085s	21.274us	7	7	100.00
V2S	acc_mem_gnt_acc_err	acc_mem_gnt_acc_err	2.950s	10.067s	14.180us	5	5	100.00
V2S	acc_non_sec_partial_wipe	acc_partial_wipe	3.760s	11.078s	263.520us	10	10	100.00
V2S	tl_intg_err	acc_sec_cm	1.611m	1.938m	4.753ms	4	4	100.00
		acc_tl_intg_err	7.320s	1.352m	671.711us	7	7	100.00
V2S	passthru_mem_tl_intg_err	acc_passthru_mem_tl_intg_err	37.570s	1.736m	375.315us	3	3	100.00
V2S	prim_fsm_check	acc_sec_cm	1.611m	1.938m	4.753ms	4	4	100.00
V2S	prim_count_check	acc_sec_cm	1.611m	1.938m	4.753ms	4	4	100.00
V2S	sec_cm_mem_scramble	acc_smoke	5.910s	20.082s	72.982us	3	3	100.00
V2S	sec_cm_data_mem_integrity	acc_dmem_err	20.040s	29.143s	2.455ms	5	5	100.00
V2S	sec_cm_instruction_mem_integrity	acc_imem_err	5.470s	13.050s	54.346us	8	8	100.00
V2S	sec_cm_bus_integrity	acc_tl_intg_err	7.320s	1.352m	671.711us	7	7	100.00
V2S	sec_cm_controller_fsm_global_esc	acc_escalate	7.920s	15.071s	46.106us	15	16	93.75
V2S	sec_cm_controller_fsm_local_esc	acc_imem_err	5.470s	13.050s	54.346us	8	8	100.00
		acc_dmem_err	20.040s	29.143s	2.455ms	5	5	100.00
		acc_zero_state_err_urnd	3.090s	11.091s	72.679us	4	4	100.00
		acc_illegal_mem_acc	2.760s	10.085s	21.274us	7	7	100.00
		acc_sec_cm	1.611m	1.938m	4.753ms	4	4	100.00
V2S	sec_cm_controller_fsm_sparse	acc_sec_cm	1.611m	1.938m	4.753ms	4	4	100.00
V2S	sec_cm_scramble_key_sideload	acc_single	12.840s	20.090s	190.027us	18	18	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	acc_imem_err	5.470s	13.050s	54.346us	8	8	100.00
		acc_dmem_err	20.040s	29.143s	2.455ms	5	5	100.00
		acc_zero_state_err_urnd	3.090s	11.091s	72.679us	4	4	100.00
		acc_illegal_mem_acc	2.760s	10.085s	21.274us	7	7	100.00
		acc_sec_cm	1.611m	1.938m	4.753ms	4	4	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	acc_sec_cm	1.611m	1.938m	4.753ms	4	4	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	acc_escalate	7.920s	15.071s	46.106us	15	16	93.75
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	acc_imem_err	5.470s	13.050s	54.346us	8	8	100.00
		acc_dmem_err	20.040s	29.143s	2.455ms	5	5	100.00
		acc_zero_state_err_urnd	3.090s	11.091s	72.679us	4	4	100.00
		acc_illegal_mem_acc	2.760s	10.085s	21.274us	7	7	100.00
		acc_sec_cm	1.611m	1.938m	4.753ms	4	4	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	acc_sec_cm	1.611m	1.938m	4.753ms	4	4	100.00
V2S	sec_cm_data_reg_sw_sca	acc_single	12.840s	20.090s	190.027us	18	18	100.00
V2S	sec_cm_ctrl_redun	acc_ctrl_redun	3.180s	11.111s	21.665us	10	10	100.00
V2S	sec_cm_pc_ctrl_flow_redun	acc_pc_ctrl_flow_redun	4.240s	11.039s	90.058us	3	3	100.00
V2S	sec_cm_rnd_bus_consistency	acc_rnd_sec_cm	39.240s	50.478s	174.558us	7	7	100.00
V2S	sec_cm_rnd_rng_digest	acc_rnd_sec_cm	39.240s	50.478s	174.558us	7	7	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	acc_rf_base_intg_err	4.910s	12.096s	68.788us	9	10	90.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	acc_sec_cm	1.611m	1.938m	4.753ms	4	4	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	acc_sec_cm	1.611m	1.938m	4.753ms	4	4	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	acc_rf_bignum_intg_err	4.740s	12.241s	309.629us	15	15	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	acc_sec_cm	1.611m	1.938m	4.753ms	4	4	100.00
V2S	sec_cm_loop_stack_ctr_redun	acc_sec_cm	1.611m	1.938m	4.753ms	4	4	100.00
V2S	sec_cm_loop_stack_addr_integrity	acc_stack_addr_integ_chk	8.420s	16.126s	77.612us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	acc_stack_addr_integ_chk	8.420s	16.126s	77.612us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	acc_sec_wipe_err	1.970s	8.053s	26.829us	3	3	100.00
V2S	sec_cm_data_mem_sec_wipe	acc_single	12.840s	20.090s	190.027us	18	18	100.00
V2S	sec_cm_instruction_mem_sec_wipe	acc_single	12.840s	20.090s	190.027us	18	18	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	acc_single	12.840s	20.090s	190.027us	18	18	100.00
V2S	sec_cm_write_mem_integrity	acc_multi	1.426m	1.879m	869.058us	12	13	92.31
V2S	sec_cm_ctrl_flow_count	acc_single	12.840s	20.090s	190.027us	18	18	100.00
V2S	sec_cm_ctrl_flow_sca	acc_single	12.840s	20.090s	190.027us	18	18	100.00
V2S	sec_cm_data_mem_sw_noaccess	acc_sw_no_acc	9.650s	17.130s	49.461us	6	7	85.71
V2S	sec_cm_key_sideload	acc_single	12.840s	20.090s	190.027us	18	18	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	acc_sec_cm	1.611m	1.938m	4.753ms	4	4	100.00
V2S		TOTAL				140	142	98.59
V3	stress_all_with_rand_reset	acc_stress_all_with_rand_reset	3.401m	4.025m	2.539ms	1	4	25.00
V3		TOTAL				1	4	25.00
		TOTAL				375	383	97.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	8	72.73
V2S	21	20	18	85.71
V3	1	1	0	0.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.43	91.24	95.29	98.89	90.62	96.94	97.22	97.79

Simulation Wall Clock Time

Target	Elapsed
build	00:07:13
run	30:46:43
cov_merge	30:47:37
cov_report	30:47:52
Total	30:47:52

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:1237) [acc_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test acc_stress_all_with_rand_reset has 2 failures.

    • 2.acc_stress_all_with_rand_reset.27036584230540234896994025001419994608236927304405703515164606514404179757413
      Line 192, in log /home/runner/_work/pavona/pavona/scratch/main/acc_standard-sim-vcs/2.acc_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 563464119 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.acc_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 563464119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.acc_stress_all_with_rand_reset.79967978106182134508898113666022931738017227726631363497820179545196861177081
      Line 194, in log /home/runner/_work/pavona/pavona/scratch/main/acc_standard-sim-vcs/3.acc_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1079680561 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.acc_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1079680561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(!$isunknown(done_o))' has 2 failures:

  • Test acc_sw_no_acc has 1 failures.

    • 3.acc_sw_no_acc.30797214916471737290668619668178962897366615613380992859667833926755948237231
      Line 120, in log /home/runner/_work/pavona/pavona/scratch/main/acc_standard-sim-vcs/3.acc_sw_no_acc/latest/run.log

            Offending '(!$isunknown(done_o))'
        UVM_ERROR @  53155369 ps: (acc_core.sv:1012) [ASSERT FAILED] DoneOKnown_A
        UVM_INFO @  53155369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test acc_multi has 1 failures.

    • 10.acc_multi.67745223530747697652117072967985284117759018106328900090918444435003538039679
      Line 147, in log /home/runner/_work/pavona/pavona/scratch/main/acc_standard-sim-vcs/10.acc_multi/latest/run.log

            Offending '(!$isunknown(done_o))'
        UVM_ERROR @  75665811 ps: (acc_core.sv:1012) [ASSERT FAILED] DoneOKnown_A
        UVM_INFO @  75665811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (acc_scoreboard.sv:547) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. has 2 failures:

  • Test acc_escalate has 1 failures.

    • 13.acc_escalate.86706839056377377133429672800849547968490900426534493149096379386647006470966
      Line 106, in log /home/runner/_work/pavona/pavona/scratch/main/acc_standard-sim-vcs/13.acc_escalate/latest/run.log

        UVM_FATAL @  85931436 ps: (acc_scoreboard.sv:547) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
        UVM_INFO @  85931436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test acc_stress_all has 1 failures.

    • 22.acc_stress_all.28405345980176111913150549990625179203626654053447487191746053788334867032533
      Line 152, in log /home/runner/_work/pavona/pavona/scratch/main/acc_standard-sim-vcs/22.acc_stress_all/latest/run.log

        UVM_FATAL @ 130737947 ps: (acc_scoreboard.sv:547) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
        UVM_INFO @ 130737947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (acc_base_vseq.sv:349) [acc_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:

  • Test acc_stress_all_with_rand_reset has 1 failures.

    • 0.acc_stress_all_with_rand_reset.28162409960615836276386562682647705308282091689597222504234621983626266295656
      Line 468, in log /home/runner/_work/pavona/pavona/scratch/main/acc_standard-sim-vcs/0.acc_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 1735691352 ps: (acc_base_vseq.sv:349) [uvm_test_top.env.virtual_sequencer.acc_imem_err_vseq] Check failed (!cfg.under_reset)
        UVM_INFO @ 1735691352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (acc_rf_base_intg_err_vseq.sv:129) [acc_rf_base_intg_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == acc_pkg::StatusLocked) has 1 failures:

  • Test acc_rf_base_intg_err has 1 failures.

    • 9.acc_rf_base_intg_err.107452808399056143540196538425717225730752308408711017284192156435243133591327
      Line 110, in log /home/runner/_work/pavona/pavona/scratch/main/acc_standard-sim-vcs/9.acc_rf_base_intg_err/latest/run.log

        UVM_FATAL @  30193211 ps: (acc_rf_base_intg_err_vseq.sv:129) [uvm_test_top.env.virtual_sequencer.acc_rf_base_intg_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == acc_pkg::StatusLocked)
        UVM_INFO @  30193211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---