ADC_CTRL Simulation Results

Sunday August 02 2026 00:03:30 UTC

GitHub Revision: 0ff052588e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	7.690s	14.099s	5.829ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	1.390s	7.149s	717.345us	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.260s	10.148s	538.574us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.054m	1.157m	52.427ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	3.140s	8.185s	1.354ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	1.510s	8.156s	598.387us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.260s	10.148s	538.574us	20	20	100.00
		adc_ctrl_csr_aliasing	3.140s	8.185s	1.354ms	5	5	100.00
V1		TOTAL				56	56	100.00
V2	filters_polled	adc_ctrl_filters_polled	9.237m	9.381m	325.639ms	4	4	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	3.090m	3.190m	484.633ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	16.675m	18.540m	495.355ms	11	11	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	10.657m	10.749m	333.892ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	10.940m	12.382m	400.899ms	16	16	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	1.571m	1.671m	189.814ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	14.823m	16.769m	541.599ms	32	33	96.97
V2	clock_gating	adc_ctrl_clock_gating	18.311m	18.724m	542.879ms	7	10	70.00
V2	poweron_counter	adc_ctrl_poweron_counter	1.650s	7.053s	3.806ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	14.560s	19.089s	41.125ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	4.000m	5.289m	134.143ms	9	9	100.00
V2	stress_all	adc_ctrl_stress_all	15.038m	16.319m	600.013ms	19	19	100.00
V2	alert_test	adc_ctrl_alert_test	1.750s	1.469m	456.831us	3	3	100.00
V2	intr_test	adc_ctrl_intr_test	1.180s	7.131s	504.047us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	1.650s	10.177s	411.799us	4	4	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	1.650s	10.177s	411.799us	4	4	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	1.390s	7.149s	717.345us	5	5	100.00
		adc_ctrl_csr_rw	1.260s	10.148s	538.574us	20	20	100.00
		adc_ctrl_csr_aliasing	3.140s	8.185s	1.354ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	2.790s	9.198s	4.730ms	3	3	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	1.390s	7.149s	717.345us	5	5	100.00
		adc_ctrl_csr_rw	1.260s	10.148s	538.574us	20	20	100.00
		adc_ctrl_csr_aliasing	3.140s	8.185s	1.354ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	2.790s	9.198s	4.730ms	3	3	100.00
V2		TOTAL				163	167	97.60
V2S	tl_intg_err	adc_ctrl_sec_cm	16.090s	1.435m	8.064ms	3	3	100.00
		adc_ctrl_tl_intg_err	6.310s	13.240s	4.360ms	6	6	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	6.310s	13.240s	4.360ms	6	6	100.00
V2S		TOTAL				9	9	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	15.990s	2.153m	86.208ms	14	14	100.00
V3		TOTAL				14	14	100.00
		TOTAL				242	246	98.37

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	14	87.50
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.38	99.05	96.03	100.00	100.00	98.64	95.95	91.98

Simulation Wall Clock Time

Target	Elapsed
build	00:07:13
run	30:46:43
cov_merge	30:47:37
cov_report	30:47:52
Total	30:47:52

Failure Buckets

• UVM_ERROR (cip_base_scoreboard.sv:259) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 2 failures:

  • Test adc_ctrl_clock_gating has 2 failures.

    • 6.adc_ctrl_clock_gating.78591991873224718839479352722057361148479883577657796155846378568833095661864
      Line 345, in log /home/runner/_work/pavona/pavona/scratch/main/adc_ctrl-sim-vcs/6.adc_ctrl_clock_gating/latest/run.log

        UVM_ERROR @ 187373813877 ps: (cip_base_scoreboard.sv:259) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
        UVM_INFO @ 187373813877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 7.adc_ctrl_clock_gating.99687934734435708375047382522502300254572982711551346076323700119682684313571
      Line 328, in log /home/runner/_work/pavona/pavona/scratch/main/adc_ctrl-sim-vcs/7.adc_ctrl_clock_gating/latest/run.log

        UVM_ERROR @ 5227682446 ps: (cip_base_scoreboard.sv:259) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
        UVM_INFO @ 5227682446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:

  • Test adc_ctrl_clock_gating has 1 failures.

    • 9.adc_ctrl_clock_gating.22714052175691254294801019501830900396456898569763722967407311938198396133393
      Line 345, in log /home/runner/_work/pavona/pavona/scratch/main/adc_ctrl-sim-vcs/9.adc_ctrl_clock_gating/latest/run.log

        UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test adc_ctrl_filters_both has 1 failures.

    • 31.adc_ctrl_filters_both.103217768117509990162511320264170111100885613790091954411882487436681081343433
      Line 360, in log /home/runner/_work/pavona/pavona/scratch/main/adc_ctrl-sim-vcs/31.adc_ctrl_filters_both/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---