AES/MASKED Simulation Results

Sunday August 02 2026 00:03:30 UTC

GitHub Revision: 0ff052588e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	0.720s	5.097s	296.901us	1	1	100.00
V1	smoke	aes_smoke	0.930s	5.109s	81.715us	1	1	100.00
V1	csr_hw_reset	aes_csr_hw_reset	1.050s	56.556s	73.715us	5	5	100.00
V1	csr_rw	aes_csr_rw	1.180s	30.088s	63.133us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	4.460s	32.086s	283.125us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	2.110s	31.088s	943.913us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	1.730s	31.086s	82.580us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	1.180s	30.088s	63.133us	20	20	100.00
		aes_csr_aliasing	2.110s	31.088s	943.913us	5	5	100.00
V1		TOTAL				57	57	100.00
V2	algorithm	aes_smoke	0.930s	5.109s	81.715us	1	1	100.00
		aes_config_error	2.370s	10.299s	968.352us	14	14	100.00
		aes_stress	0.900s	5.122s	215.155us	1	1	100.00
V2	key_length	aes_smoke	0.930s	5.109s	81.715us	1	1	100.00
		aes_config_error	2.370s	10.299s	968.352us	14	14	100.00
		aes_stress	0.900s	5.122s	215.155us	1	1	100.00
V2	back2back	aes_stress	0.900s	5.122s	215.155us	1	1	100.00
		aes_b2b	7.900s	15.592s	237.761us	3	3	100.00
V2	backpressure	aes_stress	0.900s	5.122s	215.155us	1	1	100.00
V2	multi_message	aes_smoke	0.930s	5.109s	81.715us	1	1	100.00
		aes_config_error	2.370s	10.299s	968.352us	14	14	100.00
		aes_stress	0.900s	5.122s	215.155us	1	1	100.00
		aes_alert_reset	9.220s	17.023s	1.338ms	11	11	100.00
V2	failure_test	aes_man_cfg_err	0.700s	5.109s	93.472us	1	1	100.00
		aes_config_error	2.370s	10.299s	968.352us	14	14	100.00
		aes_alert_reset	9.220s	17.023s	1.338ms	11	11	100.00
V2	trigger_clear_test	aes_clear	3.040s	9.788s	117.517us	4	4	100.00
V2	nist_test_vectors	aes_nist_vectors	6.800s	12.328s	1.209ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	9.220s	17.023s	1.338ms	11	11	100.00
V2	stress	aes_stress	0.900s	5.122s	215.155us	1	1	100.00
V2	sideload	aes_stress	0.900s	5.122s	215.155us	1	1	100.00
		aes_sideload	1.920s	9.420s	192.932us	5	5	100.00
V2	deinitialization	aes_deinit	1.860s	7.397s	435.419us	3	3	100.00
V2	stress_all	aes_stress_all	36.070s	39.995s	23.277ms	5	5	100.00
V2	alert_test	aes_alert_test	0.880s	8.423s	80.419us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	2.460s	2.503m	334.524us	4	4	100.00
V2	tl_d_illegal_access	aes_tl_errors	2.460s	2.503m	334.524us	4	4	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	1.050s	56.556s	73.715us	5	5	100.00
		aes_csr_rw	1.180s	30.088s	63.133us	20	20	100.00
		aes_csr_aliasing	2.110s	31.088s	943.913us	5	5	100.00
		aes_same_csr_outstanding	1.620s	31.091s	283.264us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	1.050s	56.556s	73.715us	5	5	100.00
		aes_csr_rw	1.180s	30.088s	63.133us	20	20	100.00
		aes_csr_aliasing	2.110s	31.088s	943.913us	5	5	100.00
		aes_same_csr_outstanding	1.620s	31.091s	283.264us	20	20	100.00
V2		TOTAL				122	122	100.00
V2S	reseeding	aes_reseed	2.420s	8.809s	95.244us	4	4	100.00
V2S	fault_inject	aes_fi	1.540s	6.203s	357.047us	1	1	100.00
		aes_control_fi	1.220s	10.308s	329.667us	149	149	100.00
		aes_control_fi_walk	55.550s	59.977s	200.000ms	363	364	99.73
		aes_cipher_fi	1.800s	9.192s	1.180ms	170	170	100.00
		aes_cipher_fi_walk	1.220s	10.160s	149.600us	500	500	100.00
		aes_core_fi_walk	8.000s	16.576s	1.316ms	21	21	100.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	1.160s	1.462m	139.489us	3	3	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	1.160s	1.462m	139.489us	3	3	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	1.160s	1.462m	139.489us	3	3	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	1.160s	1.462m	139.489us	3	3	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	2.180s	52.608s	163.442us	4	4	100.00
V2S	tl_intg_err	aes_sec_cm	3.730s	9.438s	1.381ms	3	3	100.00
		aes_tl_intg_err	3.090s	1.905m	381.574us	10	10	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	3.090s	1.905m	381.574us	10	10	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	9.220s	17.023s	1.338ms	11	11	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	1.160s	1.462m	139.489us	3	3	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	0.930s	5.109s	81.715us	1	1	100.00
		aes_stress	0.900s	5.122s	215.155us	1	1	100.00
		aes_alert_reset	9.220s	17.023s	1.338ms	11	11	100.00
		aes_core_fi	1.950s	10.196s	762.787us	22	22	100.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	1.160s	1.462m	139.489us	3	3	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	0.670s	5.109s	96.519us	1	1	100.00
		aes_stress	0.900s	5.122s	215.155us	1	1	100.00
V2S	sec_cm_key_sideload	aes_stress	0.900s	5.122s	215.155us	1	1	100.00
		aes_sideload	1.920s	9.420s	192.932us	5	5	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	0.670s	5.109s	96.519us	1	1	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	0.670s	5.109s	96.519us	1	1	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	0.670s	5.109s	96.519us	1	1	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	0.670s	5.109s	96.519us	1	1	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	0.670s	5.109s	96.519us	1	1	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	0.900s	5.122s	215.155us	1	1	100.00
V2S	sec_cm_key_masking	aes_stress	0.900s	5.122s	215.155us	1	1	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	1.540s	6.203s	357.047us	1	1	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	1.540s	6.203s	357.047us	1	1	100.00
		aes_control_fi	1.220s	10.308s	329.667us	149	149	100.00
		aes_cipher_fi	1.800s	9.192s	1.180ms	170	170	100.00
		aes_ctr_fi	2.210s	9.908s	1.255ms	23	23	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	1.540s	6.203s	357.047us	1	1	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	1.540s	6.203s	357.047us	1	1	100.00
		aes_control_fi	1.220s	10.308s	329.667us	149	149	100.00
		aes_cipher_fi	1.800s	9.192s	1.180ms	170	170	100.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	1.800s	9.192s	1.180ms	170	170	100.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	1.540s	6.203s	357.047us	1	1	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	1.540s	6.203s	357.047us	1	1	100.00
		aes_control_fi	1.220s	10.308s	329.667us	149	149	100.00
		aes_ctr_fi	2.210s	9.908s	1.255ms	23	23	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	1.540s	6.203s	357.047us	1	1	100.00
		aes_control_fi	1.220s	10.308s	329.667us	149	149	100.00
		aes_cipher_fi	1.800s	9.192s	1.180ms	170	170	100.00
		aes_ctr_fi	2.210s	9.908s	1.255ms	23	23	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	9.220s	17.023s	1.338ms	11	11	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	1.540s	6.203s	357.047us	1	1	100.00
		aes_control_fi	1.220s	10.308s	329.667us	149	149	100.00
		aes_cipher_fi	1.800s	9.192s	1.180ms	170	170	100.00
		aes_ctr_fi	2.210s	9.908s	1.255ms	23	23	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	1.540s	6.203s	357.047us	1	1	100.00
		aes_control_fi	1.220s	10.308s	329.667us	149	149	100.00
		aes_cipher_fi	1.800s	9.192s	1.180ms	170	170	100.00
		aes_ctr_fi	2.210s	9.908s	1.255ms	23	23	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	1.540s	6.203s	357.047us	1	1	100.00
		aes_control_fi	1.220s	10.308s	329.667us	149	149	100.00
		aes_ctr_fi	2.210s	9.908s	1.255ms	23	23	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	1.540s	6.203s	357.047us	1	1	100.00
		aes_control_fi	1.220s	10.308s	329.667us	149	149	100.00
		aes_cipher_fi	1.800s	9.192s	1.180ms	170	170	100.00
V2S		TOTAL				1274	1275	99.92
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset				0	0	--
V3		TOTAL				0	0	--
		TOTAL				1453	1454	99.93

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	14	14	13	92.86
V3	1	0	0	0.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.51	99.63	97.48	99.73	100.00	99.64	98.38	94.67

Simulation Wall Clock Time

Target	Elapsed
build	00:07:13
run	30:46:43
cov_merge	30:47:37
cov_report	30:47:52
Total	30:47:52

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test aes_control_fi_walk has 1 failures.

    • 156.aes_control_fi_walk.96857408487236193309458094153923451831186618297904795940934678451011824904788
      Line 140, in log /home/runner/_work/pavona/pavona/scratch/main/aes_masked-sim-vcs/156.aes_control_fi_walk/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---