AES/UNMASKED Simulation Results

Sunday August 02 2026 00:03:30 UTC

GitHub Revision: 0ff052588e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Max Wall Clock Simulated Time Passing Total Pass Rate
V1 wake_up aes_wake_up 0.800s 10.080s 120.420us 1 1 100.00
V1 smoke aes_smoke 0.630s 11.105s 82.502us 1 1 100.00
V1 csr_hw_reset aes_csr_hw_reset 0.580s 13.098s 98.480us 5 5 100.00
V1 csr_rw aes_csr_rw 0.600s 16.117s 65.197us 20 20 100.00
V1 csr_bit_bash aes_csr_bit_bash 2.710s 13.105s 291.138us 5 5 100.00
V1 csr_aliasing aes_csr_aliasing 1.340s 16.117s 375.052us 5 5 100.00
V1 csr_mem_rw_with_rand_reset aes_csr_mem_rw_with_rand_reset 0.960s 12.105s 75.217us 3 3 100.00
V1 regwen_csr_and_corresponding_lockable_csr aes_csr_rw 0.600s 16.117s 65.197us 20 20 100.00
aes_csr_aliasing 1.340s 16.117s 375.052us 5 5 100.00
V1 TOTAL 40 40 100.00
V2 algorithm aes_smoke 0.630s 11.105s 82.502us 1 1 100.00
aes_config_error 1.230s 11.558s 312.119us 15 15 100.00
aes_stress 1.260s 10.736s 104.633us 5 5 100.00
V2 key_length aes_smoke 0.630s 11.105s 82.502us 1 1 100.00
aes_config_error 1.230s 11.558s 312.119us 15 15 100.00
aes_stress 1.260s 10.736s 104.633us 5 5 100.00
V2 back2back aes_stress 1.260s 10.736s 104.633us 5 5 100.00
aes_b2b 2.660s 12.111s 202.887us 3 3 100.00
V2 backpressure aes_stress 1.260s 10.736s 104.633us 5 5 100.00
V2 multi_message aes_smoke 0.630s 11.105s 82.502us 1 1 100.00
aes_config_error 1.230s 11.558s 312.119us 15 15 100.00
aes_stress 1.260s 10.736s 104.633us 5 5 100.00
aes_alert_reset 1.220s 11.572s 249.125us 6 6 100.00
V2 failure_test aes_man_cfg_err 0.590s 10.080s 233.552us 1 1 100.00
aes_config_error 1.230s 11.558s 312.119us 15 15 100.00
aes_alert_reset 1.220s 11.572s 249.125us 6 6 100.00
V2 trigger_clear_test aes_clear 1.230s 11.208s 76.419us 4 4 100.00
V2 nist_test_vectors aes_nist_vectors 1.830s 11.088s 301.330us 1 1 100.00
V2 reset_recovery aes_alert_reset 1.220s 11.572s 249.125us 6 6 100.00
V2 stress aes_stress 1.260s 10.736s 104.633us 5 5 100.00
V2 sideload aes_stress 1.260s 10.736s 104.633us 5 5 100.00
aes_sideload 1.010s 11.587s 115.211us 6 6 100.00
V2 deinitialization aes_deinit 2.320s 11.741s 530.953us 3 3 100.00
V2 stress_all aes_stress_all 11.420s 19.876s 1.046ms 6 6 100.00
V2 alert_test aes_alert_test 0.570s 9.667s 68.927us 3 3 100.00
V2 tl_d_oob_addr_access aes_tl_errors 1.460s 12.272s 272.393us 3 3 100.00
V2 tl_d_illegal_access aes_tl_errors 1.460s 12.272s 272.393us 3 3 100.00
V2 tl_d_outstanding_access aes_csr_hw_reset 0.580s 13.098s 98.480us 5 5 100.00
aes_csr_rw 0.600s 16.117s 65.197us 20 20 100.00
aes_csr_aliasing 1.340s 16.117s 375.052us 5 5 100.00
aes_same_csr_outstanding 0.950s 12.104s 375.272us 20 20 100.00
V2 tl_d_partial_access aes_csr_hw_reset 0.580s 13.098s 98.480us 5 5 100.00
aes_csr_rw 0.600s 16.117s 65.197us 20 20 100.00
aes_csr_aliasing 1.340s 16.117s 375.052us 5 5 100.00
aes_same_csr_outstanding 0.950s 12.104s 375.272us 20 20 100.00
V2 TOTAL 76 76 100.00
V2S reseeding aes_reseed 2.040s 12.314s 726.549us 4 4 100.00
V2S fault_inject aes_fi 0.870s 11.293s 312.081us 1 1 100.00
aes_control_fi 0.940s 14.286s 471.572us 135 135 100.00
aes_control_fi_walk 1.270s 14.543s 913.696us 383 383 100.00
aes_cipher_fi 0.930s 11.848s 273.097us 93 93 100.00
aes_cipher_fi_walk 1.970s 14.532s 3.562ms 503 503 100.00
aes_core_fi_walk 1.000s 11.337s 194.601us 26 26 100.00
V2S shadow_reg_update_error aes_shadow_reg_errors 0.700s 12.104s 149.087us 3 3 100.00
V2S shadow_reg_read_clear_staged_value aes_shadow_reg_errors 0.700s 12.104s 149.087us 3 3 100.00
V2S shadow_reg_storage_error aes_shadow_reg_errors 0.700s 12.104s 149.087us 3 3 100.00
V2S shadowed_reset_glitch aes_shadow_reg_errors 0.700s 12.104s 149.087us 3 3 100.00
V2S shadow_reg_update_error_with_csr_rw aes_shadow_reg_errors_with_csr_rw 1.110s 14.120s 313.667us 3 3 100.00
V2S tl_intg_err aes_sec_cm 1.660s 10.321s 555.800us 3 3 100.00
aes_tl_intg_err 1.490s 17.133s 369.876us 11 11 100.00
V2S sec_cm_bus_integrity aes_tl_intg_err 1.490s 17.133s 369.876us 11 11 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi aes_alert_reset 1.220s 11.572s 249.125us 6 6 100.00
V2S sec_cm_main_config_shadow aes_shadow_reg_errors 0.700s 12.104s 149.087us 3 3 100.00
V2S sec_cm_main_config_sparse aes_smoke 0.630s 11.105s 82.502us 1 1 100.00
aes_stress 1.260s 10.736s 104.633us 5 5 100.00
aes_alert_reset 1.220s 11.572s 249.125us 6 6 100.00
aes_core_fi 0.880s 10.916s 124.567us 15 15 100.00
V2S sec_cm_aux_config_shadow aes_shadow_reg_errors 0.700s 12.104s 149.087us 3 3 100.00
V2S sec_cm_aux_config_regwen aes_readability 0.590s 10.079s 94.897us 1 1 100.00
aes_stress 1.260s 10.736s 104.633us 5 5 100.00
V2S sec_cm_key_sideload aes_stress 1.260s 10.736s 104.633us 5 5 100.00
aes_sideload 1.010s 11.587s 115.211us 6 6 100.00
V2S sec_cm_key_sw_unreadable aes_readability 0.590s 10.079s 94.897us 1 1 100.00
V2S sec_cm_data_reg_sw_unreadable aes_readability 0.590s 10.079s 94.897us 1 1 100.00
V2S sec_cm_key_sec_wipe aes_readability 0.590s 10.079s 94.897us 1 1 100.00
V2S sec_cm_iv_config_sec_wipe aes_readability 0.590s 10.079s 94.897us 1 1 100.00
V2S sec_cm_data_reg_sec_wipe aes_readability 0.590s 10.079s 94.897us 1 1 100.00
V2S sec_cm_data_reg_key_sca aes_stress 1.260s 10.736s 104.633us 5 5 100.00
V2S sec_cm_key_masking aes_stress 1.260s 10.736s 104.633us 5 5 100.00
V2S sec_cm_main_fsm_sparse aes_fi 0.870s 11.293s 312.081us 1 1 100.00
V2S sec_cm_main_fsm_redun aes_fi 0.870s 11.293s 312.081us 1 1 100.00
aes_control_fi 0.940s 14.286s 471.572us 135 135 100.00
aes_cipher_fi 0.930s 11.848s 273.097us 93 93 100.00
aes_ctr_fi 0.770s 10.783s 56.099us 27 27 100.00
V2S sec_cm_cipher_fsm_sparse aes_fi 0.870s 11.293s 312.081us 1 1 100.00
V2S sec_cm_cipher_fsm_redun aes_fi 0.870s 11.293s 312.081us 1 1 100.00
aes_control_fi 0.940s 14.286s 471.572us 135 135 100.00
aes_cipher_fi 0.930s 11.848s 273.097us 93 93 100.00
V2S sec_cm_cipher_ctr_redun aes_cipher_fi 0.930s 11.848s 273.097us 93 93 100.00
V2S sec_cm_ctr_fsm_sparse aes_fi 0.870s 11.293s 312.081us 1 1 100.00
V2S sec_cm_ctr_fsm_redun aes_fi 0.870s 11.293s 312.081us 1 1 100.00
aes_control_fi 0.940s 14.286s 471.572us 135 135 100.00
aes_ctr_fi 0.770s 10.783s 56.099us 27 27 100.00
V2S sec_cm_ctrl_sparse aes_fi 0.870s 11.293s 312.081us 1 1 100.00
aes_control_fi 0.940s 14.286s 471.572us 135 135 100.00
aes_cipher_fi 0.930s 11.848s 273.097us 93 93 100.00
aes_ctr_fi 0.770s 10.783s 56.099us 27 27 100.00
V2S sec_cm_main_fsm_global_esc aes_alert_reset 1.220s 11.572s 249.125us 6 6 100.00
V2S sec_cm_main_fsm_local_esc aes_fi 0.870s 11.293s 312.081us 1 1 100.00
aes_control_fi 0.940s 14.286s 471.572us 135 135 100.00
aes_cipher_fi 0.930s 11.848s 273.097us 93 93 100.00
aes_ctr_fi 0.770s 10.783s 56.099us 27 27 100.00
V2S sec_cm_cipher_fsm_local_esc aes_fi 0.870s 11.293s 312.081us 1 1 100.00
aes_control_fi 0.940s 14.286s 471.572us 135 135 100.00
aes_cipher_fi 0.930s 11.848s 273.097us 93 93 100.00
aes_ctr_fi 0.770s 10.783s 56.099us 27 27 100.00
V2S sec_cm_ctr_fsm_local_esc aes_fi 0.870s 11.293s 312.081us 1 1 100.00
aes_control_fi 0.940s 14.286s 471.572us 135 135 100.00
aes_ctr_fi 0.770s 10.783s 56.099us 27 27 100.00
V2S sec_cm_data_reg_local_esc aes_fi 0.870s 11.293s 312.081us 1 1 100.00
aes_control_fi 0.940s 14.286s 471.572us 135 135 100.00
aes_cipher_fi 0.930s 11.848s 273.097us 93 93 100.00
V2S TOTAL 1208 1208 100.00
V3 stress_all_with_rand_reset aes_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 1324 1324 100.00

Testplan Progress

Items Total Written Passing Progress
V1 7 7 7 100.00
V2 13 13 13 100.00
V2S 14 14 14 100.00
V3 1 0 0 0.00

Coverage Results

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
96.90 97.44 96.52 100.00 92.68 98.41 98.11 95.15

Simulation Wall Clock Time

Target Elapsed
build 00:07:13
run 30:46:43
cov_merge 30:47:37
cov_report 30:47:52
Total 30:47:52