ALERT_HANDLER/DRAGONFLY Simulation Results

Sunday August 02 2026 00:03:30 UTC

GitHub Revision: 0ff052588e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	17.790s	22.179s	826.290us	1	1	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	8.410s	4.170m	111.800us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	12.370s	3.953m	575.746us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	9.294m	10.411m	10.212ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	3.601m	5.038m	2.405ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	16.410s	2.487m	173.792us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	12.370s	3.953m	575.746us	20	20	100.00
		alert_handler_csr_aliasing	3.601m	5.038m	2.405ms	5	5	100.00
V1		TOTAL				56	56	100.00
V2	esc_accum	alert_handler_esc_alert_accum	2.071m	2.142m	3.679ms	1	1	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	36.090s	3.937m	1.011ms	4	4	100.00
V2	entropy	alert_handler_entropy	39.878m	42.907m	226.931ms	8	8	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.160m	5.837m	1.217ms	11	11	100.00
V2	clk_skew	alert_handler_smoke	17.790s	22.179s	826.290us	1	1	100.00
V2	random_alerts	alert_handler_random_alerts	1.120m	1.191m	2.658ms	1	1	100.00
V2	random_classes	alert_handler_random_classes	40.990s	3.453m	1.142ms	4	4	100.00
V2	ping_timeout	alert_handler_ping_timeout	8.315m	11.109m	106.844ms	13	19	68.42
V2	lpg	alert_handler_lpg	49.391m	53.900m	272.349ms	16	16	100.00
		alert_handler_lpg_stub_clk	30.036m	30.636m	100.700ms	4	4	100.00
V2	stress_all	alert_handler_stress_all	56.770m	58.584m	1.191s	23	23	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	21.380s	1.902m	3.865ms	3	3	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	5.780s	4.387m	47.889us	7	7	100.00
V2	intr_test	alert_handler_intr_test	1.930s	5.537m	11.436us	6	6	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	44.550s	6.804m	481.150us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	44.550s	6.804m	481.150us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	8.410s	4.170m	111.800us	5	5	100.00
		alert_handler_csr_rw	12.370s	3.953m	575.746us	20	20	100.00
		alert_handler_csr_aliasing	3.601m	5.038m	2.405ms	5	5	100.00
		alert_handler_same_csr_outstanding	56.130s	3.121m	1.472ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	8.410s	4.170m	111.800us	5	5	100.00
		alert_handler_csr_rw	12.370s	3.953m	575.746us	20	20	100.00
		alert_handler_csr_aliasing	3.601m	5.038m	2.405ms	5	5	100.00
		alert_handler_same_csr_outstanding	56.130s	3.121m	1.472ms	20	20	100.00
V2		TOTAL				141	147	95.92
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	6.928m	9.291m	11.955ms	14	14	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	6.928m	9.291m	11.955ms	14	14	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	6.928m	9.291m	11.955ms	14	14	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	6.928m	9.291m	11.955ms	14	14	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	19.562m	21.161m	14.327ms	12	12	100.00
V2S	tl_intg_err	alert_handler_sec_cm	25.860s	3.286m	592.349us	5	5	100.00
		alert_handler_tl_intg_err	1.343m	6.122m	1.034ms	38	38	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.343m	6.122m	1.034ms	38	38	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	6.928m	9.291m	11.955ms	14	14	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	17.790s	22.179s	826.290us	1	1	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	17.790s	22.179s	826.290us	1	1	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	17.790s	22.179s	826.290us	1	1	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	17.790s	22.179s	826.290us	1	1	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.160m	5.837m	1.217ms	11	11	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	49.391m	53.900m	272.349ms	16	16	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.160m	5.837m	1.217ms	11	11	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	39.878m	42.907m	226.931ms	8	8	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	39.878m	42.907m	226.931ms	8	8	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	25.860s	3.286m	592.349us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	25.860s	3.286m	592.349us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	25.860s	3.286m	592.349us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	25.860s	3.286m	592.349us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	25.860s	3.286m	592.349us	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	25.860s	3.286m	592.349us	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	25.860s	3.286m	592.349us	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	25.860s	3.286m	592.349us	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	25.860s	3.286m	592.349us	5	5	100.00
V2S		TOTAL				69	69	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	8.962m	12.142m	17.614ms	10	12	83.33
V3		TOTAL				10	12	83.33
		TOTAL				276	284	97.18

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	14	93.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.18	99.99	98.72	97.37	100.00	99.99	98.92	99.25

Simulation Wall Clock Time

Target	Elapsed
build	00:07:13
run	30:46:43
cov_merge	30:47:37
cov_report	30:47:52
Total	30:47:52

Failure Buckets

• UVM_ERROR (alert_handler_scoreboard.sv:483) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state has 6 failures:

  • Test alert_handler_ping_timeout has 6 failures.

    • 12.alert_handler_ping_timeout.93076164504206499298088270389352770385829142748418993399596836676496025198690
      Line 97, in log /home/runner/_work/pavona/pavona/scratch/main/alert_handler_top_dragonfly-sim-vcs/12.alert_handler_ping_timeout/latest/run.log

        UVM_ERROR @ 970651532 ps: (alert_handler_scoreboard.sv:483) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state
        UVM_INFO @ 970651532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 13.alert_handler_ping_timeout.105750697114899032788564927347952595864204073305922761459703799607976181618326
      Line 109, in log /home/runner/_work/pavona/pavona/scratch/main/alert_handler_top_dragonfly-sim-vcs/13.alert_handler_ping_timeout/latest/run.log

        UVM_ERROR @ 2344693341 ps: (alert_handler_scoreboard.sv:483) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state
        UVM_INFO @ 2344693341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 4 more failures.

• UVM_ERROR (cip_base_vseq.sv:1237) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 9.alert_handler_stress_all_with_rand_reset.102139334756684637287813876892667486452299649914057462168206159456698665508158
      Line 183, in log /home/runner/_work/pavona/pavona/scratch/main/alert_handler_top_dragonfly-sim-vcs/9.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5895612586 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 5895612586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1150) [alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 10.alert_handler_stress_all_with_rand_reset.22687919098919392604779954604330927083000415090475906464156936013522676679796
      Line 89, in log /home/runner/_work/pavona/pavona/scratch/main/alert_handler_top_dragonfly-sim-vcs/10.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  35608004 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @  35608004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---