ALERT_HANDLER/EGRET Simulation Results

Sunday August 02 2026 00:03:30 UTC

GitHub Revision: 0ff052588e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	15.090s	33.172s	1.323ms	1	1	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	9.630s	1.619m	143.347us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	5.190s	1.185m	60.043us	3	3	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	5.391m	6.241m	7.729ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	3.385m	3.873m	13.719ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	11.620s	1.952m	179.444us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	5.190s	1.185m	60.043us	3	3	100.00
		alert_handler_csr_aliasing	3.385m	3.873m	13.719ms	5	5	100.00
V1		TOTAL				39	39	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.080s	20.122s	487.557us	1	1	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	5.160s	18.117s	312.563us	1	1	100.00
V2	entropy	alert_handler_entropy	32.508m	35.594m	37.335ms	7	7	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	53.430s	4.853m	1.797ms	9	9	100.00
V2	clk_skew	alert_handler_smoke	15.090s	33.172s	1.323ms	1	1	100.00
V2	random_alerts	alert_handler_random_alerts	14.850s	30.170s	1.743ms	1	1	100.00
V2	random_classes	alert_handler_random_classes	6.020s	24.134s	192.495us	1	1	100.00
V2	ping_timeout	alert_handler_ping_timeout	9.536m	12.060m	70.024ms	15	18	83.33
V2	lpg	alert_handler_lpg	40.546m	40.769m	116.117ms	15	15	100.00
		alert_handler_lpg_stub_clk	17.928m	18.850m	76.077ms	4	4	100.00
V2	stress_all	alert_handler_stress_all	54.463m	54.687m	271.229ms	24	24	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	36.930s	1.535m	2.124ms	3	3	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	3.480s	2.802m	38.356us	7	7	100.00
V2	intr_test	alert_handler_intr_test	1.620s	1.468m	18.912us	5	5	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	18.960s	1.818m	643.987us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	18.960s	1.818m	643.987us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	9.630s	1.619m	143.347us	5	5	100.00
		alert_handler_csr_rw	5.190s	1.185m	60.043us	3	3	100.00
		alert_handler_csr_aliasing	3.385m	3.873m	13.719ms	5	5	100.00
		alert_handler_same_csr_outstanding	46.130s	2.352m	2.726ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	9.630s	1.619m	143.347us	5	5	100.00
		alert_handler_csr_rw	5.190s	1.185m	60.043us	3	3	100.00
		alert_handler_csr_aliasing	3.385m	3.873m	13.719ms	5	5	100.00
		alert_handler_same_csr_outstanding	46.130s	2.352m	2.726ms	20	20	100.00
V2		TOTAL				133	136	97.79
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	4.208m	5.373m	4.920ms	15	15	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	4.208m	5.373m	4.920ms	15	15	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	4.208m	5.373m	4.920ms	15	15	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	4.208m	5.373m	4.920ms	15	15	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	12.180m	13.407m	17.284ms	15	15	100.00
V2S	tl_intg_err	alert_handler_sec_cm	31.580s	3.836m	1.217ms	5	5	100.00
		alert_handler_tl_intg_err	45.460s	2.353m	4.549ms	35	35	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	45.460s	2.353m	4.549ms	35	35	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	4.208m	5.373m	4.920ms	15	15	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	15.090s	33.172s	1.323ms	1	1	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	15.090s	33.172s	1.323ms	1	1	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	15.090s	33.172s	1.323ms	1	1	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	15.090s	33.172s	1.323ms	1	1	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	53.430s	4.853m	1.797ms	9	9	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	40.546m	40.769m	116.117ms	15	15	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	53.430s	4.853m	1.797ms	9	9	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	32.508m	35.594m	37.335ms	7	7	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	32.508m	35.594m	37.335ms	7	7	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	31.580s	3.836m	1.217ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	31.580s	3.836m	1.217ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	31.580s	3.836m	1.217ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	31.580s	3.836m	1.217ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	31.580s	3.836m	1.217ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	31.580s	3.836m	1.217ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	31.580s	3.836m	1.217ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	31.580s	3.836m	1.217ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	31.580s	3.836m	1.217ms	5	5	100.00
V2S		TOTAL				70	70	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	5.969m	8.706m	11.275ms	8	8	100.00
V3		TOTAL				8	8	100.00
		TOTAL				250	253	98.81

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	14	93.33
V2S	4	4	4	100.00
V3	1	1	1	100.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.15	99.99	98.84	97.06	100.00	99.99	98.88	99.32

Simulation Wall Clock Time

Target	Elapsed
build	00:07:13
run	30:46:43
cov_merge	30:47:37
cov_report	30:47:52
Total	30:47:52

Failure Buckets

• UVM_ERROR (alert_handler_scoreboard.sv:483) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state has 3 failures:
  • Test alert_handler_ping_timeout has 3 failures.

    • 11.alert_handler_ping_timeout.50907589071104999353205550847332895990338298067769105218757149195011185139170
      Line 118, in log /home/runner/_work/pavona/pavona/scratch/main/alert_handler_top_egret-sim-vcs/11.alert_handler_ping_timeout/latest/run.log

        UVM_ERROR @ 18702344916 ps: (alert_handler_scoreboard.sv:483) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state
        UVM_INFO @ 18702344916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 13.alert_handler_ping_timeout.106812914807488945508223861533300244165509228977731682479441562577583469331478
      Line 103, in log /home/runner/_work/pavona/pavona/scratch/main/alert_handler_top_egret-sim-vcs/13.alert_handler_ping_timeout/latest/run.log

        UVM_ERROR @ 10660183225 ps: (alert_handler_scoreboard.sv:483) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state
        UVM_INFO @ 10660183225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.