AON_TIMER Simulation Results

Sunday August 02 2026 00:03:30 UTC

GitHub Revision: 0ff052588e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.630s	19.311s	582.435us	5	5	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	1.570s	10.235s	723.082us	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.560s	10.236s	436.684us	3	3	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	5.370s	14.137s	14.262ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.310s	10.052s	615.249us	3	3	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.180s	11.060s	569.619us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.560s	10.236s	436.684us	3	3	100.00
		aon_timer_csr_aliasing	1.310s	10.052s	615.249us	3	3	100.00
V1	mem_walk	aon_timer_mem_walk	1.030s	12.236s	501.758us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.000s	11.233s	495.847us	5	5	100.00
V1		TOTAL				51	51	100.00
V2	prescaler	aon_timer_prescaler	8.500s	29.523s	31.668ms	1	1	100.00
V2	jump	aon_timer_jump	1.570s	18.339s	654.505us	5	5	100.00
V2	stress_all	aon_timer_stress_all	1.468m	1.598m	114.169ms	3	3	100.00
V2	alert_test	aon_timer_alert_test	1.210s	10.273s	340.375us	3	3	100.00
V2	intr_test	aon_timer_intr_test	1.140s	11.230s	493.031us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	1.970s	13.072s	422.620us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	1.970s	13.072s	422.620us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	1.570s	10.235s	723.082us	5	5	100.00
		aon_timer_csr_rw	1.560s	10.236s	436.684us	3	3	100.00
		aon_timer_csr_aliasing	1.310s	10.052s	615.249us	3	3	100.00
		aon_timer_same_csr_outstanding	3.690s	12.098s	2.775ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	1.570s	10.235s	723.082us	5	5	100.00
		aon_timer_csr_rw	1.560s	10.236s	436.684us	3	3	100.00
		aon_timer_csr_aliasing	1.310s	10.052s	615.249us	3	3	100.00
		aon_timer_same_csr_outstanding	3.690s	12.098s	2.775ms	20	20	100.00
V2		TOTAL				102	102	100.00
V2S	tl_intg_err	aon_timer_sec_cm	5.430s	16.154s	4.731ms	3	3	100.00
		aon_timer_tl_intg_err	4.760s	14.242s	7.874ms	3	3	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	4.760s	14.242s	7.874ms	3	3	100.00
V2S		TOTAL				6	6	100.00
V3	max_threshold	aon_timer_smoke_max_thold	1.430s	19.323s	597.144us	3	3	100.00
V3	min_threshold	aon_timer_smoke_min_thold	1.320s	19.322s	704.740us	5	5	100.00
V3	wkup_count_hi_cdc	aon_timer_wkup_count_cdc_hi	2.030s	14.316s	3.788ms	3	3	100.00
V3	custom_intr	aon_timer_custom_intr	1.250s	19.343s	560.501us	10	10	100.00
V3	alternating_on_off	aon_timer_alternating_enable_on_off	10.390s	21.378s	4.160ms	4	4	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	37.970s	45.490s	103.252ms	8	8	100.00
V3		TOTAL				33	33	100.00
		TOTAL				192	192	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	7	7	7	100.00
V2S	2	2	2	100.00
V3	6	6	6	100.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.89	99.09	99.05	100.00	--	98.56	96.67	100.00

Simulation Wall Clock Time

Target	Elapsed
build	00:07:13
run	30:46:43
cov_merge	30:47:37
cov_report	30:47:52
Total	30:47:52