0ff052588e| Stage | Name | Tests | Max Job Runtime | Max Wall Clock | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|---|
| V1 | chip_sw_uart_tx_rx | chip_sw_uart_tx_rx | 0 | 0 | -- | |||
| V1 | chip_sw_uart_rx_overflow | chip_sw_uart_tx_rx | 0 | 0 | -- | |||
| V1 | chip_sw_uart_rand_baudrate | chip_sw_uart_rand_baudrate | 0 | 0 | -- | |||
| V1 | chip_sw_uart_tx_rx_alt_clk_freq | chip_sw_uart_tx_rx_alt_clk_freq | 0 | 0 | -- | |||
| V1 | chip_sw_gpio_out | chip_sw_gpio | 14.571m | 15.482m | 297.039us | 5 | 5 | 100.00 |
| V1 | chip_sw_gpio_in | chip_sw_gpio | 14.571m | 15.482m | 297.039us | 5 | 5 | 100.00 |
| V1 | chip_sw_gpio_irq | chip_sw_gpio | 14.571m | 15.482m | 297.039us | 5 | 5 | 100.00 |
| V1 | chip_sw_example_tests | chip_sw_example_rom | 5.122m | 7.986m | 124.247us | 4 | 4 | 100.00 |
| chip_sw_example_manufacturer | 2.547m | 2.547m | 0 | 1 | 0.00 | |||
| chip_sw_example_concurrency | 6.739m | 9.770m | 168.717us | 1 | 1 | 100.00 | ||
| chip_sw_example_flash | 0 | 0 | -- | |||||
| chip_sw_uart_smoketest_signed | 0 | 0 | -- | |||||
| V1 | csr_hw_reset | chip_csr_hw_reset | 0 | 0 | -- | |||
| V1 | csr_rw | chip_csr_rw | 0 | 0 | -- | |||
| V1 | csr_bit_bash | chip_csr_bit_bash | 0 | 1 | 0.00 | |||
| V1 | csr_aliasing | chip_csr_aliasing | 0 | 1 | 0.00 | |||
| V1 | csr_mem_rw_with_rand_reset | chip_csr_mem_rw_with_rand_reset | 0 | 0 | -- | |||
| V1 | regwen_csr_and_corresponding_lockable_csr | chip_csr_aliasing | 0 | 1 | 0.00 | |||
| chip_csr_rw | 0 | 0 | -- | |||||
| V1 | xbar_smoke | xbar_smoke | 45.880s | 5.433m | 64.714us | 100 | 100 | 100.00 |
| V1 | TOTAL | 110 | 113 | 97.35 | ||||
| V2 | chip_sw_spi_device_flash_mode | chip_sw_uart_tx_rx_bootstrap | 0 | 0 | -- | |||
| V2 | chip_sw_spi_device_pass_through | chip_sw_spi_device_pass_through | 12.911m | 15.884m | 409.817us | 0 | 1 | 0.00 |
| V2 | chip_sw_spi_device_pass_through_collision | chip_sw_spi_device_pass_through_collision | 9.252m | 12.774m | 180.606us | 0 | 1 | 0.00 |
| V2 | chip_sw_spi_device_tpm | chip_sw_spi_device_tpm | 0 | 0 | -- | |||
| V2 | chip_sw_spi_host_tx_rx | chip_sw_spi_host_tx_rx | 0 | 0 | -- | |||
| V2 | chip_sw_i2c_host_tx_rx | chip_sw_i2c_host_tx_rx | 0 | 0 | -- | |||
| V2 | chip_sw_i2c_device_tx_rx | chip_sw_i2c_device_tx_rx | 0 | 0 | -- | |||
| V2 | chip_pin_mux | chip_padctrl_attributes | 3.120s | 20.429s | 0 | 10 | 0.00 | |
| V2 | chip_padctrl_attributes | chip_padctrl_attributes | 3.120s | 20.429s | 0 | 10 | 0.00 | |
| V2 | chip_sw_sleep_pin_mio_dio_val | chip_sw_sleep_pin_mio_dio_val | 0 | 0 | -- | |||
| V2 | chip_sw_sleep_pin_wake | chip_sw_sleep_pin_wake | 0 | 0 | -- | |||
| V2 | chip_sw_sleep_pin_retention | chip_sw_sleep_pin_retention | 0 | 0 | -- | |||
| V2 | chip_sw_mbx_smoke | chip_sw_mbx_smoke | 0 | 0 | -- | |||
| V2 | chip_sw_data_integrity | chip_sw_data_integrity_escalation | 0 | 0 | -- | |||
| V2 | chip_sw_instruction_integrity | chip_sw_data_integrity_escalation | 0 | 0 | -- | |||
| V2 | chip_jtag_csr_rw | chip_jtag_csr_rw | 3.557m | 3.891m | 117.016us | 0 | 1 | 0.00 |
| V2 | chip_jtag_mem_access | chip_jtag_mem_access | 4.300m | 4.643m | 117.009us | 0 | 1 | 0.00 |
| V2 | chip_rv_dm_ndm_reset_req | chip_rv_dm_ndm_reset_req | 13.198m | 13.834m | 309.926us | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 0 | 0 | -- | |||
| V2 | chip_rv_dm_access_after_wakeup | chip_sw_rv_dm_access_after_wakeup | 0 | 0 | -- | |||
| V2 | chip_rv_dm_lc_disabled | chip_rv_dm_lc_disabled | 20.835m | 21.337m | 900.486us | 4 | 7 | 57.14 |
| V2 | chip_sw_timer | chip_sw_rv_timer_irq | 11.235m | 12.056m | 266.166us | 1 | 1 | 100.00 |
| V2 | chip_sw_aon_timer_wakeup_irq | chip_sw_aon_timer_irq | 16.899m | 17.662m | 486.578us | 0 | 1 | 0.00 |
| V2 | chip_sw_aon_timer_sleep_wakeup | chip_sw_pwrmgr_smoketest | 0 | 0 | -- | |||
| V2 | chip_sw_aon_timer_wdog_bark_irq | chip_sw_aon_timer_irq | 16.899m | 17.662m | 486.578us | 0 | 1 | 0.00 |
| V2 | chip_sw_aon_timer_wdog_lc_escalate | chip_sw_aon_timer_wdog_lc_escalate | 18.310m | 19.093m | 385.588us | 1 | 1 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 7.890m | 8.513m | 182.233us | 0 | 1 | 0.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 7.890m | 8.513m | 182.233us | 0 | 1 | 0.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_sleep_pause | chip_sw_aon_timer_sleep_wdog_sleep_pause | 16.448m | 17.106m | 2.310ms | 3 | 3 | 100.00 |
| V2 | chip_sw_plic_all_irqs | chip_plic_all_irqs_0 | 19.320m | 20.042m | 326.752us | 11 | 11 | 100.00 |
| chip_plic_all_irqs_10 | 16.611m | 17.322m | 296.474us | 10 | 10 | 100.00 | ||
| V2 | chip_sw_plic_sw_irq | chip_sw_plic_sw_irq | 7.132m | 7.699m | 164.549us | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_idle_trans | chip_sw_acc_randomness | 12.737m | 13.419m | 244.568us | 1 | 1 | 100.00 |
| chip_sw_aes_idle | 8.270m | 8.812m | 164.961us | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_idle | 7.977m | 8.629m | 177.869us | 1 | 1 | 100.00 | ||
| chip_sw_kmac_idle | 7.717m | 8.411m | 163.288us | 1 | 1 | 100.00 | ||
| V2 | chip_sw_clkmgr_off_trans | chip_sw_clkmgr_off_aes_trans | 8.036m | 8.632m | 184.672us | 0 | 1 | 0.00 |
| chip_sw_clkmgr_off_hmac_trans | 7.159m | 7.749m | 184.608us | 0 | 1 | 0.00 | ||
| chip_sw_clkmgr_off_kmac_trans | 7.601m | 8.221m | 184.544us | 0 | 1 | 0.00 | ||
| chip_sw_clkmgr_off_acc_trans | 6.998m | 7.603m | 184.656us | 0 | 1 | 0.00 | ||
| V2 | chip_sw_clkmgr_off_peri | chip_sw_clkmgr_off_peri | 0 | 0 | -- | |||
| V2 | chip_sw_clkmgr_jitter | chip_sw_acc_ecdsa_op_irq_jitter_en | 2.024h | 2.059h | 1.472ms | 1 | 1 | 100.00 |
| chip_sw_aes_enc_jitter_en | 8.610m | 9.180m | 172.897us | 1 | 1 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en | 7.801m | 8.496m | 173.543us | 1 | 1 | 100.00 | ||
| chip_sw_keymgr_dpe_key_derivation_jitter_en | 13.732m | 14.389m | 304.371us | 0 | 1 | 0.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 9.463m | 10.099m | 188.430us | 1 | 1 | 100.00 | ||
| chip_sw_clkmgr_jitter | 7.899m | 8.446m | 161.162us | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 0 | 0 | -- | |||||
| chip_sw_edn_entropy_reqs_jitter | 0 | 0 | -- | |||||
| V2 | chip_sw_clkmgr_extended_range | chip_sw_clkmgr_jitter_reduced_freq | 17.621m | 18.584m | 1.963ms | 1 | 1 | 100.00 |
| chip_sw_acc_ecdsa_op_irq_jitter_en_reduced_freq | 4.525h | 4.590h | 20.713ms | 1 | 1 | 100.00 | ||
| chip_sw_aes_enc_jitter_en_reduced_freq | 17.718m | 18.532m | 2.134ms | 1 | 1 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en_reduced_freq | 20.181m | 20.958m | 2.143ms | 1 | 1 | 100.00 | ||
| chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq | 36.772m | 37.781m | 3.916ms | 0 | 1 | 0.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en_reduced_freq | 18.156m | 18.954m | 2.355ms | 1 | 1 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq | 36.359m | 37.409m | 4.391ms | 1 | 1 | 100.00 | ||
| chip_sw_csrng_edn_concurrency_reduced_freq | 3.631h | 3.683h | 17.595ms | 3 | 4 | 75.00 | ||
| V2 | chip_sw_clkmgr_deep_sleep_frequency | chip_sw_ast_clk_outputs | 0 | 0 | -- | |||
| V2 | chip_sw_clkmgr_sleep_frequency | chip_sw_clkmgr_sleep_frequency | 0 | 0 | -- | |||
| V2 | chip_sw_clkmgr_reset_frequency | chip_sw_clkmgr_reset_frequency | 0 | 0 | -- | |||
| V2 | chip_sw_clkmgr_escalation_reset | chip_sw_all_escalation_resets | 54.590m | 55.958m | 950.689us | 53 | 56 | 94.64 |
| V2 | chip_sw_pwrmgr_external_full_reset | chip_sw_pwrmgr_full_aon_reset | 16.192m | 16.807m | 505.571us | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_all_wake_ups | chip_sw_pwrmgr_random_sleep_all_wake_ups | 0 | 0 | -- | |||
| V2 | chip_sw_pwrmgr_normal_sleep_all_wake_ups | chip_sw_pwrmgr_normal_sleep_all_wake_ups | 0 | 0 | -- | |||
| V2 | chip_sw_pwrmgr_sleep_all_reset_reqs | chip_sw_aon_timer_wdog_bite_reset | 7.890m | 8.513m | 182.233us | 0 | 1 | 0.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_all_wake_ups | chip_sw_pwrmgr_deep_sleep_all_wake_ups | 0 | 0 | -- | |||
| V2 | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 0 | 0 | -- | |||
| V2 | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | 0 | 0 | -- | |||
| V2 | chip_sw_pwrmgr_wdog_reset | chip_sw_pwrmgr_wdog_reset | 0 | 0 | -- | |||
| V2 | chip_sw_pwrmgr_aon_power_glitch_reset | chip_sw_pwrmgr_full_aon_reset | 16.192m | 16.807m | 505.571us | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_main_power_glitch_reset | chip_sw_pwrmgr_main_power_glitch_reset | 0 | 0 | -- | |||
| V2 | chip_sw_pwrmgr_random_sleep_power_glitch_reset | chip_sw_pwrmgr_random_sleep_power_glitch_reset | 0 | 0 | -- | |||
| V2 | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 0 | 0 | -- | |||
| V2 | chip_sw_pwrmgr_sleep_power_glitch_reset | chip_sw_pwrmgr_sleep_power_glitch_reset | 0 | 0 | -- | |||
| V2 | chip_sw_pwrmgr_random_sleep_all_reset_reqs | chip_sw_pwrmgr_random_sleep_all_reset_reqs | 0 | 0 | -- | |||
| V2 | chip_sw_pwrmgr_sleep_disabled | chip_sw_pwrmgr_sleep_disabled | 0 | 0 | -- | |||
| V2 | chip_sw_pwrmgr_escalation_reset | chip_sw_all_escalation_resets | 54.590m | 55.958m | 950.689us | 53 | 56 | 94.64 |
| V2 | chip_sw_rstmgr_non_sys_reset_info | chip_sw_pwrmgr_smoketest | 0 | 0 | -- | |||
| V2 | chip_sw_rstmgr_sys_reset_info | chip_rv_dm_ndm_reset_req | 13.198m | 13.834m | 309.926us | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_cpu_info | chip_sw_rstmgr_cpu_info | 15.542m | 16.462m | 412.128us | 0 | 1 | 0.00 |
| V2 | chip_sw_rstmgr_sw_req_reset | chip_sw_rstmgr_sw_req | 12.878m | 13.540m | 304.422us | 1 | 1 | 100.00 |
| V2 | chip_sw_rstmgr_alert_info | chip_sw_rstmgr_alert_info | 16.708m | 17.581m | 343.949us | 0 | 1 | 0.00 |
| V2 | chip_sw_rstmgr_sw_rst | chip_sw_rstmgr_sw_rst | 7.090m | 7.734m | 163.470us | 1 | 1 | 100.00 |
| V2 | chip_sw_rstmgr_escalation_reset | chip_sw_all_escalation_resets | 54.590m | 55.958m | 950.689us | 53 | 56 | 94.64 |
| V2 | chip_sw_alert_handler_alerts | chip_sw_alert_test | 0 | 0 | -- | |||
| V2 | chip_sw_alert_handler_escalations | chip_sw_alert_handler_escalation | 0 | 0 | -- | |||
| V2 | chip_sw_all_escalation_resets | chip_sw_all_escalation_resets | 54.590m | 55.958m | 950.689us | 53 | 56 | 94.64 |
| V2 | chip_sw_alert_handler_irqs | chip_plic_all_irqs | 0 | 0 | -- | |||
| V2 | chip_sw_alert_handler_entropy | chip_sw_alert_handler_entropy | 0 | 0 | -- | |||
| V2 | chip_sw_alert_handler_crashdump | chip_sw_rstmgr_alert_info | 16.708m | 17.581m | 343.949us | 0 | 1 | 0.00 |
| V2 | chip_sw_alert_handler_ping_timeout | chip_sw_alert_handler_ping_timeout | 16.067m | 16.705m | 368.103us | 13 | 13 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_alerts | chip_sw_alert_handler_lpg_sleep_mode_alerts | 0 | 0 | -- | |||
| V2 | chip_sw_alert_handler_lpg_sleep_mode_pings | chip_sw_alert_handler_lpg_sleep_mode_pings | 0 | 0 | -- | |||
| V2 | chip_sw_alert_handler_lpg_clock_off | chip_sw_alert_handler_lpg_clkoff | 0 | 0 | -- | |||
| V2 | chip_sw_alert_handler_lpg_reset_toggle | chip_sw_alert_handler_lpg_reset_toggle | 0 | 0 | -- | |||
| V2 | chip_sw_alert_handler_reverse_ping_in_deep_sleep | chip_sw_alert_handler_reverse_ping_in_deep_sleep | 0 | 0 | -- | |||
| V2 | chip_sw_lc_ctrl_alert_handler_escalation | chip_sw_alert_handler_escalation | 0 | 0 | -- | |||
| V2 | chip_sw_lc_ctrl_jtag_access | chip_sw_lc_ctrl_transition | 43.598m | 45.405m | 1.020ms | 4 | 4 | 100.00 |
| V2 | chip_sw_lc_ctrl_otp_hw_cfg | chip_sw_lc_ctrl_otp_hw_cfg | 7.476m | 11.118m | 167.865us | 1 | 1 | 100.00 |
| V2 | chip_sw_lc_ctrl_init | chip_sw_lc_ctrl_transition | 43.598m | 45.405m | 1.020ms | 4 | 4 | 100.00 |
| V2 | chip_sw_lc_ctrl_transitions | chip_sw_lc_ctrl_transition | 43.598m | 45.405m | 1.020ms | 4 | 4 | 100.00 |
| V2 | chip_sw_lc_ctrl_kmac_req | chip_sw_lc_ctrl_transition | 43.598m | 45.405m | 1.020ms | 4 | 4 | 100.00 |
| V2 | chip_sw_lc_ctrl_key_div | chip_sw_keymgr_dpe_key_derivation_prod | 14.041m | 14.722m | 304.263us | 0 | 1 | 0.00 |
| V2 | chip_sw_lc_ctrl_broadcast | chip_sw_lc_ctrl_transition | 43.598m | 45.405m | 1.020ms | 4 | 4 | 100.00 |
| chip_sw_keymgr_dpe_key_derivation | 11.752m | 12.417m | 304.344us | 0 | 1 | 0.00 | ||
| chip_sw_rom_ctrl_integrity_check | 44.842m | 46.013m | 1.294ms | 1 | 1 | 100.00 | ||
| chip_prim_tl_access | 27.175m | 27.761m | 1.094ms | 3 | 5 | 60.00 | ||
| chip_rv_dm_lc_disabled | 20.835m | 21.337m | 900.486us | 4 | 7 | 57.14 | ||
| chip_sw_sram_ctrl_execution_main | 0 | 0 | -- | |||||
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 0 | 0 | -- | |||||
| chip_sw_otp_ctrl_lc_signals_dev | 0 | 0 | -- | |||||
| chip_sw_otp_ctrl_lc_signals_prod | 0 | 0 | -- | |||||
| chip_sw_otp_ctrl_lc_signals_rma | 0 | 0 | -- | |||||
| V2 | chip_sw_aes_enc | chip_sw_aes_enc | 7.470m | 8.078m | 172.854us | 1 | 1 | 100.00 |
| chip_sw_aes_enc_jitter_en | 8.610m | 9.180m | 172.897us | 1 | 1 | 100.00 | ||
| V2 | chip_sw_aes_entropy | chip_sw_aes_entropy | 7.872m | 8.512m | 164.289us | 1 | 1 | 100.00 |
| V2 | chip_sw_aes_idle | chip_sw_aes_idle | 8.270m | 8.812m | 164.961us | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_sideload | chip_sw_keymgr_sideload_aes | 0 | 0 | -- | |||
| V2 | chip_sw_hmac_enc | chip_sw_hmac_enc | 7.316m | 7.995m | 173.578us | 1 | 1 | 100.00 |
| chip_sw_hmac_enc_jitter_en | 7.801m | 8.496m | 173.543us | 1 | 1 | 100.00 | ||
| V2 | chip_sw_hmac_idle | chip_sw_hmac_enc_idle | 7.977m | 8.629m | 177.869us | 1 | 1 | 100.00 |
| V2 | chip_sw_kmac_enc | chip_sw_kmac_mode_cshake | 7.290m | 7.894m | 166.734us | 1 | 1 | 100.00 |
| chip_sw_kmac_mode_kmac | 7.393m | 7.995m | 188.578us | 1 | 1 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 9.463m | 10.099m | 188.430us | 1 | 1 | 100.00 | ||
| V2 | chip_sw_kmac_app_keymgr | chip_sw_keymgr_dpe_key_derivation | 11.752m | 12.417m | 304.344us | 0 | 1 | 0.00 |
| V2 | chip_sw_kmac_app_lc | chip_sw_lc_ctrl_transition | 43.598m | 45.405m | 1.020ms | 4 | 4 | 100.00 |
| V2 | chip_sw_kmac_app_rom | chip_sw_kmac_app_rom | 23.053s | 23.053s | 0 | 1 | 0.00 | |
| V2 | chip_sw_kmac_entropy | chip_sw_kmac_entropy | 12.542m | 15.213m | 228.309us | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_idle | chip_sw_kmac_idle | 7.717m | 8.411m | 163.288us | 1 | 1 | 100.00 |
| V2 | chip_sw_entropy_src_csrng | chip_sw_entropy_src_csrng | 15.654m | 16.305m | 270.989us | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_edn_cmd | chip_sw_entropy_src_csrng | 15.654m | 16.305m | 270.989us | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_fuse_en_sw_app_read | chip_sw_csrng_fuse_en_sw_app_read_test | 0 | 0 | -- | |||
| V2 | chip_sw_csrng_known_answer_tests | chip_sw_csrng_kat_test | 6.730m | 7.328m | 167.220us | 1 | 1 | 100.00 |
| V2 | chip_sw_edn_entropy_reqs | chip_sw_csrng_edn_concurrency | 1.061h | 1.083h | 939.465us | 3 | 3 | 100.00 |
| chip_sw_edn_entropy_reqs | 0 | 0 | -- | |||||
| V2 | chip_sw_keymgr_dpe_key_derivation | chip_sw_keymgr_dpe_key_derivation | 11.752m | 12.417m | 304.344us | 0 | 1 | 0.00 |
| chip_sw_keymgr_dpe_key_derivation_jitter_en | 13.732m | 14.389m | 304.371us | 0 | 1 | 0.00 | ||
| V2 | chip_sw_keymgr_sideload_kmac | chip_sw_keymgr_sideload_kmac | 0 | 0 | -- | |||
| V2 | chip_sw_keymgr_sideload_aes | chip_sw_keymgr_sideload_aes | 0 | 0 | -- | |||
| V2 | chip_sw_keymgr_sideload_acc | chip_sw_keymgr_sideload_acc | 0 | 0 | -- | |||
| V2 | chip_sw_acc_op | chip_sw_acc_ecdsa_op_irq | 1.899h | 1.933h | 1.462ms | 1 | 1 | 100.00 |
| chip_sw_acc_ecdsa_op_irq_jitter_en | 2.024h | 2.059h | 1.472ms | 1 | 1 | 100.00 | ||
| V2 | chip_sw_acc_rnd_entropy | chip_sw_acc_randomness | 12.737m | 13.419m | 244.568us | 1 | 1 | 100.00 |
| V2 | chip_sw_acc_urnd_entropy | chip_sw_acc_randomness | 12.737m | 13.419m | 244.568us | 1 | 1 | 100.00 |
| V2 | chip_sw_acc_idle | chip_sw_acc_randomness | 12.737m | 13.419m | 244.568us | 1 | 1 | 100.00 |
| V2 | chip_sw_acc_mem_scramble | chip_sw_acc_mem_scramble | 14.537m | 15.204m | 278.431us | 1 | 1 | 100.00 |
| V2 | chip_sw_rom_access | chip_sw_rom_ctrl_integrity_check | 44.842m | 46.013m | 1.294ms | 1 | 1 | 100.00 |
| V2 | chip_sw_rom_ctrl_integrity_check | chip_sw_rom_ctrl_integrity_check | 44.842m | 46.013m | 1.294ms | 1 | 1 | 100.00 |
| V2 | chip_sw_sram_scrambled_access | chip_sw_sram_ctrl_scrambled_access | 18.189m | 18.877m | 349.009us | 3 | 3 | 100.00 |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 0 | 0 | -- | |||||
| V2 | chip_sw_sleep_sram_ret_contents | chip_sw_sleep_sram_ret_contents | 0 | 0 | -- | |||
| V2 | chip_sw_sram_execution | chip_sw_sram_ctrl_execution_main | 0 | 0 | -- | |||
| V2 | chip_sw_sram_lc_escalation | chip_sw_all_escalation_resets | 54.590m | 55.958m | 950.689us | 53 | 56 | 94.64 |
| chip_sw_data_integrity_escalation | 0 | 0 | -- | |||||
| V2 | chip_otp_ctrl_init | chip_sw_lc_ctrl_transition | 43.598m | 45.405m | 1.020ms | 4 | 4 | 100.00 |
| V2 | chip_sw_otp_ctrl_keys | chip_sw_acc_mem_scramble | 14.537m | 15.204m | 278.431us | 1 | 1 | 100.00 |
| chip_sw_keymgr_dpe_key_derivation | 11.752m | 12.417m | 304.344us | 0 | 1 | 0.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 18.189m | 18.877m | 349.009us | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 8.933m | 9.722m | 188.332us | 1 | 1 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_entropy | chip_sw_acc_mem_scramble | 14.537m | 15.204m | 278.431us | 1 | 1 | 100.00 |
| chip_sw_keymgr_dpe_key_derivation | 11.752m | 12.417m | 304.344us | 0 | 1 | 0.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 18.189m | 18.877m | 349.009us | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 8.933m | 9.722m | 188.332us | 1 | 1 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_program | chip_sw_lc_ctrl_transition | 43.598m | 45.405m | 1.020ms | 4 | 4 | 100.00 |
| V2 | chip_sw_otp_ctrl_program_error | chip_sw_lc_ctrl_program_error | 0 | 0 | -- | |||
| V2 | chip_sw_otp_ctrl_hw_cfg | chip_sw_lc_ctrl_otp_hw_cfg | 7.476m | 11.118m | 167.865us | 1 | 1 | 100.00 |
| V2 | chip_sw_otp_ctrl_lc_signals | chip_sw_lc_ctrl_transition | 43.598m | 45.405m | 1.020ms | 4 | 4 | 100.00 |
| chip_prim_tl_access | 27.175m | 27.761m | 1.094ms | 3 | 5 | 60.00 | ||
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 0 | 0 | -- | |||||
| chip_sw_otp_ctrl_lc_signals_dev | 0 | 0 | -- | |||||
| chip_sw_otp_ctrl_lc_signals_prod | 0 | 0 | -- | |||||
| chip_sw_otp_ctrl_lc_signals_rma | 0 | 0 | -- | |||||
| V2 | chip_sw_otp_prim_tl_access | chip_prim_tl_access | 27.175m | 27.761m | 1.094ms | 3 | 5 | 60.00 |
| V2 | chip_sw_otp_ctrl_nvm_cnt | chip_sw_otp_ctrl_nvm_cnt | 0 | 0 | -- | |||
| V2 | chip_sw_otp_ctrl_sw_parts | chip_sw_otp_ctrl_sw_parts | 0 | 0 | -- | |||
| V2 | chip_sw_ast_clk_outputs | chip_sw_ast_clk_outputs | 0 | 0 | -- | |||
| V2 | chip_sw_ast_clk_rst_inputs | chip_sw_ast_clk_rst_inputs | 0 | 0 | -- | |||
| V2 | chip_sw_ast_sys_clk_jitter | chip_sw_acc_ecdsa_op_irq_jitter_en | 2.024h | 2.059h | 1.472ms | 1 | 1 | 100.00 |
| chip_sw_aes_enc_jitter_en | 8.610m | 9.180m | 172.897us | 1 | 1 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en | 7.801m | 8.496m | 173.543us | 1 | 1 | 100.00 | ||
| chip_sw_keymgr_dpe_key_derivation_jitter_en | 13.732m | 14.389m | 304.371us | 0 | 1 | 0.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 9.463m | 10.099m | 188.430us | 1 | 1 | 100.00 | ||
| chip_sw_clkmgr_jitter | 7.899m | 8.446m | 161.162us | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 0 | 0 | -- | |||||
| chip_sw_edn_entropy_reqs_jitter | 0 | 0 | -- | |||||
| V2 | chip_sw_ast_alerts | chip_sw_sensor_ctrl_alert | 0 | 0 | -- | |||
| V2 | chip_sw_sensor_ctrl_ast_alerts | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 0 | 0 | -- | |||
| chip_sw_sensor_ctrl_alert | 0 | 0 | -- | |||||
| V2 | chip_sw_sensor_ctrl_ast_status | chip_sw_sensor_ctrl_status | 0 | 0 | -- | |||
| V2 | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 0 | 0 | -- | |||
| V2 | chip_sw_soc_proxy_external_reset_requests | chip_sw_soc_proxy_smoketest | 7.494m | 8.282m | 156.416us | 0 | 1 | 0.00 |
| V2 | chip_sw_soc_proxy_external_irqs | chip_sw_soc_proxy_smoketest | 7.494m | 8.282m | 156.416us | 0 | 1 | 0.00 |
| V2 | chip_sw_soc_proxy_external_wakeup_requests | chip_sw_soc_proxy_external_wakeup | 7.057m | 7.731m | 157.584us | 0 | 1 | 0.00 |
| V2 | chip_sw_soc_proxy_gpios | chip_sw_soc_proxy_gpios | 9.039m | 9.668m | 183.207us | 0 | 1 | 0.00 |
| V2 | chip_sw_nmi_irq | chip_sw_rv_core_ibex_nmi_irq | 13.198m | 13.886m | 268.863us | 0 | 1 | 0.00 |
| V2 | chip_sw_rv_core_ibex_rnd | chip_sw_rv_core_ibex_rnd | 7.165m | 7.745m | 185.568us | 0 | 1 | 0.00 |
| V2 | chip_sw_rv_core_ibex_address_translation | chip_sw_rv_core_ibex_address_translation | 8.270m | 8.812m | 179.851us | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_core_ibex_icache_scrambled_access | chip_sw_rv_core_ibex_icache_invalidate | 8.933m | 9.722m | 188.332us | 1 | 1 | 100.00 |
| V2 | chip_sw_rv_core_ibex_fault_dump | chip_sw_rstmgr_cpu_info | 15.542m | 16.462m | 412.128us | 0 | 1 | 0.00 |
| V2 | chip_sw_rv_core_ibex_double_fault | chip_sw_rstmgr_cpu_info | 15.542m | 16.462m | 412.128us | 0 | 1 | 0.00 |
| V2 | chip_sw_smoketest | chip_sw_aes_smoketest | 8.160m | 8.961m | 172.870us | 1 | 1 | 100.00 |
| chip_sw_aon_timer_smoketest | 9.204m | 9.946m | 181.476us | 1 | 1 | 100.00 | ||
| chip_sw_clkmgr_smoketest | 7.060m | 7.644m | 162.066us | 1 | 1 | 100.00 | ||
| chip_sw_csrng_smoketest | 7.025m | 7.627m | 163.775us | 1 | 1 | 100.00 | ||
| chip_sw_gpio_smoketest | 8.885m | 9.462m | 192.846us | 1 | 1 | 100.00 | ||
| chip_sw_hmac_smoketest | 8.630m | 9.312m | 194.048us | 1 | 1 | 100.00 | ||
| chip_sw_kmac_smoketest | 8.839m | 9.463m | 185.340us | 1 | 1 | 100.00 | ||
| chip_sw_acc_smoketest | 12.570m | 13.210m | 226.808us | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_smoketest | 6.371m | 6.927m | 165.966us | 1 | 1 | 100.00 | ||
| chip_sw_rv_plic_smoketest | 7.158m | 7.783m | 163.903us | 1 | 1 | 100.00 | ||
| chip_sw_rv_timer_smoketest | 9.604m | 10.305m | 266.245us | 1 | 1 | 100.00 | ||
| chip_sw_rstmgr_smoketest | 7.116m | 7.750m | 160.880us | 1 | 1 | 100.00 | ||
| chip_sw_sram_ctrl_smoketest | 5.828m | 6.463m | 163.898us | 1 | 1 | 100.00 | ||
| chip_sw_uart_smoketest | 8.774m | 9.453m | 174.981us | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_smoketest | 0 | 0 | -- | |||||
| V2 | chip_sw_rom_functests | rom_keymgr_functest | 0 | 0 | -- | |||
| V2 | chip_sw_signed | chip_sw_uart_smoketest_signed | 0 | 0 | -- | |||
| V2 | chip_sw_boot | chip_sw_uart_tx_rx_bootstrap | 0 | 0 | -- | |||
| V2 | chip_sw_secure_boot | base_rom_e2e_smoke | 13.051s | 13.051s | 0 | 1 | 0.00 | |
| V2 | chip_lc_scrap | chip_sw_lc_ctrl_rma_to_scrap | 9.320m | 10.732m | 219.717us | 3 | 3 | 100.00 |
| chip_sw_lc_ctrl_raw_to_scrap | 8.411m | 11.617m | 230.112us | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_test_locked0_to_scrap | 7.170m | 10.429m | 221.395us | 3 | 3 | 100.00 | ||
| chip_sw_lc_ctrl_rand_to_scrap | 8.365m | 10.930m | 232.431us | 3 | 3 | 100.00 | ||
| V2 | chip_lc_test_locked | chip_sw_lc_walkthrough_testunlocks | 0 | 1 | 0.00 | |||
| chip_rv_dm_lc_disabled | 20.835m | 21.337m | 900.486us | 4 | 7 | 57.14 | ||
| V2 | chip_sw_lc_walkthrough | chip_sw_lc_walkthrough_dev | 51.776m | 53.973m | 1.072ms | 4 | 4 | 100.00 |
| chip_sw_lc_walkthrough_prod | 52.303m | 53.789m | 1.070ms | 4 | 4 | 100.00 | ||
| chip_sw_lc_walkthrough_prodend | 42.723m | 44.500m | 876.580us | 4 | 4 | 100.00 | ||
| chip_sw_lc_walkthrough_rma | 43.876m | 45.012m | 882.819us | 4 | 4 | 100.00 | ||
| chip_sw_lc_walkthrough_testunlocks | 0 | 1 | 0.00 | |||||
| V2 | chip_sw_lc_ctrl_volatile_raw_unlock | chip_sw_lc_ctrl_volatile_raw_unlock | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz | 0 | 1 | 0.00 | |||||
| rom_volatile_raw_unlock | 0 | 0 | -- | |||||
| V2 | chip_sw_rom_raw_unlock | rom_raw_unlock | 0 | 0 | -- | |||
| V2 | chip_sw_exit_test_unlocked_bootstrap | chip_sw_exit_test_unlocked_bootstrap | 0 | 0 | -- | |||
| V2 | chip_sw_inject_scramble_seed | chip_sw_inject_scramble_seed | 0 | 0 | -- | |||
| V2 | tl_d_oob_addr_access | chip_tl_errors | 3.090s | 21.094s | 0 | 30 | 0.00 | |
| V2 | tl_d_illegal_access | chip_tl_errors | 3.090s | 21.094s | 0 | 30 | 0.00 | |
| V2 | tl_d_outstanding_access | chip_csr_aliasing | 0 | 1 | 0.00 | |||
| chip_same_csr_outstanding | 0 | 1 | 0.00 | |||||
| chip_csr_hw_reset | 0 | 0 | -- | |||||
| chip_csr_rw | 0 | 0 | -- | |||||
| V2 | tl_d_partial_access | chip_csr_aliasing | 0 | 1 | 0.00 | |||
| chip_same_csr_outstanding | 0 | 1 | 0.00 | |||||
| chip_csr_hw_reset | 0 | 0 | -- | |||||
| chip_csr_rw | 0 | 0 | -- | |||||
| V2 | xbar_base_random_sequence | xbar_random | 1.306m | 4.305m | 104.122us | 4 | 4 | 100.00 |
| V2 | xbar_random_delay | xbar_smoke_zero_delays | 16.720s | 4.590m | 12.364us | 100 | 100 | 100.00 |
| xbar_smoke_large_delays | 6.082m | 8.613m | 2.437ms | 4 | 4 | 100.00 | ||
| xbar_smoke_slow_rsp | 10.474m | 11.531m | 2.265ms | 100 | 100 | 100.00 | ||
| xbar_random_zero_delays | 3.197m | 5.123m | 83.927us | 100 | 100 | 100.00 | ||
| xbar_random_large_delays | 39.311m | 39.676m | 14.088ms | 100 | 100 | 100.00 | ||
| xbar_random_slow_rsp | 59.019m | 59.775m | 14.570ms | 99 | 100 | 99.00 | ||
| V2 | xbar_unmapped_address | xbar_unmapped_addr | 4.306m | 8.054m | 234.373us | 100 | 100 | 100.00 |
| xbar_error_and_unmapped_addr | 2.278m | 5.876m | 161.668us | 3 | 3 | 100.00 | ||
| V2 | xbar_error_cases | xbar_error_random | 7.094m | 9.063m | 494.001us | 100 | 100 | 100.00 |
| xbar_error_and_unmapped_addr | 2.278m | 5.876m | 161.668us | 3 | 3 | 100.00 | ||
| V2 | xbar_all_access_same_device | xbar_access_same_device | 10.489m | 14.770m | 883.431us | 13 | 13 | 100.00 |
| xbar_access_same_device_slow_rsp | 49.452m | 51.893m | 12.648ms | 3 | 3 | 100.00 | ||
| V2 | xbar_all_hosts_use_same_source_id | xbar_same_source | 3.824m | 7.361m | 393.264us | 4 | 4 | 100.00 |
| V2 | xbar_stress_all | xbar_stress_all | 25.613m | 29.358m | 2.368ms | 5 | 5 | 100.00 |
| xbar_stress_all_with_error | 27.880m | 31.394m | 3.016ms | 10 | 10 | 100.00 | ||
| V2 | xbar_stress_with_reset | xbar_stress_all_with_rand_reset | 42.228m | 43.306m | 3.313ms | 17 | 17 | 100.00 |
| xbar_stress_all_with_reset_error | 45.417m | 51.145m | 4.257ms | 23 | 23 | 100.00 | ||
| V2 | rom_e2e_smoke | rom_e2e_smoke | 0 | 0 | -- | |||
| V2 | rom_e2e_shutdown_output | rom_e2e_shutdown_output | 0 | 0 | -- | |||
| V2 | rom_e2e_shutdown_exception_c | rom_e2e_shutdown_exception_c | 0 | 0 | -- | |||
| V2 | rom_e2e_boot_policy_valid | rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 0 | 0 | -- | |||
| rom_e2e_boot_policy_valid_a_good_b_good_dev | 0 | 0 | -- | |||||
| rom_e2e_boot_policy_valid_a_good_b_good_prod | 0 | 0 | -- | |||||
| rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 0 | 0 | -- | |||||
| rom_e2e_boot_policy_valid_a_good_b_good_rma | 0 | 0 | -- | |||||
| rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 0 | 0 | -- | |||||
| rom_e2e_boot_policy_valid_a_good_b_bad_dev | 0 | 0 | -- | |||||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod | 0 | 0 | -- | |||||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 0 | 0 | -- | |||||
| rom_e2e_boot_policy_valid_a_good_b_bad_rma | 0 | 0 | -- | |||||
| rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 0 | 0 | -- | |||||
| rom_e2e_boot_policy_valid_a_bad_b_good_dev | 0 | 0 | -- | |||||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod | 0 | 0 | -- | |||||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 0 | 0 | -- | |||||
| rom_e2e_boot_policy_valid_a_bad_b_good_rma | 0 | 0 | -- | |||||
| V2 | rom_e2e_sigverify_always | rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 0 | 0 | -- | |||
| rom_e2e_sigverify_always_a_bad_b_bad_dev | 0 | 0 | -- | |||||
| rom_e2e_sigverify_always_a_bad_b_bad_prod | 0 | 0 | -- | |||||
| rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 0 | 0 | -- | |||||
| rom_e2e_sigverify_always_a_bad_b_bad_rma | 0 | 0 | -- | |||||
| rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 0 | 0 | -- | |||||
| rom_e2e_sigverify_always_a_bad_b_nothing_dev | 0 | 0 | -- | |||||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod | 0 | 0 | -- | |||||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 0 | 0 | -- | |||||
| rom_e2e_sigverify_always_a_bad_b_nothing_rma | 0 | 0 | -- | |||||
| rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 0 | 0 | -- | |||||
| rom_e2e_sigverify_always_a_nothing_b_bad_dev | 0 | 0 | -- | |||||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod | 0 | 0 | -- | |||||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 0 | 0 | -- | |||||
| rom_e2e_sigverify_always_a_nothing_b_bad_rma | 0 | 0 | -- | |||||
| V2 | rom_e2e_asm_init | rom_e2e_asm_init_test_unlocked0 | 0 | 0 | -- | |||
| rom_e2e_asm_init_dev | 0 | 0 | -- | |||||
| rom_e2e_asm_init_prod | 0 | 0 | -- | |||||
| rom_e2e_asm_init_prod_end | 0 | 0 | -- | |||||
| rom_e2e_asm_init_rma | 0 | 0 | -- | |||||
| V2 | rom_e2e_keymgr_init | rom_e2e_keymgr_init_rom_ext_meas | 0 | 0 | -- | |||
| rom_e2e_keymgr_init_rom_ext_no_meas | 0 | 0 | -- | |||||
| rom_e2e_keymgr_init_rom_ext_invalid_meas | 0 | 0 | -- | |||||
| V2 | rom_e2e_static_critical | rom_e2e_static_critical | 0 | 0 | -- | |||
| V2 | TOTAL | 991 | 1068 | 92.79 | ||||
| V2S | chip_sw_aes_masking_off | chip_sw_aes_masking_off | 10.116m | 10.680m | 193.229us | 3 | 3 | 100.00 |
| V2S | chip_sw_rv_core_ibex_lockstep_glitch | chip_sw_rv_core_ibex_lockstep_glitch | 6.029m | 6.543m | 136.333us | 6 | 7 | 85.71 |
| V2S | TOTAL | 9 | 10 | 90.00 | ||||
| V3 | chip_sw_spi_device_pass_through_flash_model | chip_sw_spi_device_pass_through_flash_model | 0 | 0 | -- | |||
| V3 | chip_sw_spi_device_output_when_disabled_or_sleeping | chip_sw_spi_device_output_when_disabled_or_sleeping | 0 | 0 | -- | |||
| V3 | chip_rv_dm_perform_debug | rom_e2e_jtag_debug_test_unlocked0 | 0 | 0 | -- | |||
| rom_e2e_jtag_debug_dev | 0 | 0 | -- | |||||
| rom_e2e_jtag_debug_rma | 0 | 0 | -- | |||||
| V3 | chip_sw_rv_dm_access_after_hw_reset | chip_sw_rv_dm_access_after_escalation_reset | 0 | 0 | -- | |||
| V3 | chip_sw_plic_alerts | chip_sw_all_escalation_resets | 54.590m | 55.958m | 950.689us | 53 | 56 | 94.64 |
| V3 | chip_sw_lc_ctrl_kmac_error | chip_sw_lc_ctrl_kmac_error | 0 | 0 | -- | |||
| V3 | chip_sw_csrng_edn_error | chip_sw_csrng_edn_error | 0 | 0 | -- | |||
| V3 | chip_sw_keymgr_sideload_kmac_error | chip_sw_keymgr_sideload_kmac_error | 0 | 0 | -- | |||
| V3 | chip_sw_rom_ctrl_kmac_error | chip_sw_rom_ctrl_kmac_error | 0 | 0 | -- | |||
| V3 | chip_sw_otp_ctrl_vendor_test_csr_access | chip_sw_otp_ctrl_vendor_test_csr_access | 0 | 0 | -- | |||
| V3 | chip_sw_otp_ctrl_escalation | chip_sw_otp_ctrl_escalation | 7.663m | 10.883m | 176.248us | 0 | 1 | 0.00 |
| V3 | chip_sw_rv_core_ibex_alerts | chip_sw_rv_core_ibex_alerts | 0 | 0 | -- | |||
| V3 | chip_sw_coremark | chip_sw_coremark | 0 | 0 | -- | |||
| V3 | chip_sw_power_max_load | chip_sw_power_virus | 0 | 0 | -- | |||
| V3 | rom_e2e_debug | rom_e2e_jtag_debug_test_unlocked0 | 0 | 0 | -- | |||
| rom_e2e_jtag_debug_dev | 0 | 0 | -- | |||||
| rom_e2e_jtag_debug_rma | 0 | 0 | -- | |||||
| V3 | rom_e2e_jtag_inject | rom_e2e_jtag_inject_test_unlocked0 | 0 | 0 | -- | |||
| rom_e2e_jtag_inject_dev | 0 | 0 | -- | |||||
| rom_e2e_jtag_inject_rma | 0 | 0 | -- | |||||
| V3 | rom_bootstrap_rma | rom_bootstrap_rma | 0 | 0 | -- | |||
| V3 | rom_e2e_weak_straps | rom_e2e_weak_straps | 0 | 0 | -- | |||
| V3 | rom_e2e_self_hash | rom_e2e_self_hash | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 1 | 0.00 | ||||
| Unmapped tests | chip_sw_rstmgr_rst_cnsty_escalation | 44.585m | 47.397m | 950.702us | 4 | 4 | 100.00 | |
| chip_sw_entropy_src_kat_test | 6.973m | 7.595m | 163.254us | 1 | 1 | 100.00 | ||
| chip_sw_entropy_src_ast_rng_req | 6.914m | 7.561m | 160.998us | 1 | 1 | 100.00 | ||
| chip_sw_dma_inline_hashing | 9.280m | 9.949m | 207.617us | 3 | 3 | 100.00 | ||
| chip_sw_dma_abort | 9.595m | 10.482m | 211.736us | 0 | 1 | 0.00 | ||
| chip_sw_entropy_src_smoketest | 10.464m | 11.101m | 202.022us | 3 | 3 | 100.00 | ||
| chip_sw_mbx_smoketest | 22.098m | 22.888m | 420.838us | 8 | 8 | 100.00 | ||
| TOTAL | 1130 | 1213 | 93.16 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 7 | 7 | 6 | 85.71 |
| V1 | 15 | 7 | 4 | 26.67 |
| V2 | 220 | 115 | 81 | 36.82 |
| V2S | 2 | 2 | 1 | 50.00 |
| V3 | 21 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 68.92 | 66.61 | 71.04 | 64.12 | 37.50 | 77.15 | 77.03 | 88.99 |
| Target | Elapsed |
|---|---|
| build | 00:07:13 |
| run | 30:46:43 |
| cov_merge | 30:47:37 |
| cov_report | 30:47:52 |
| Total | 30:47:52 |
UVM_WARNING @ * us: [BDTYP] Cannot create an object of type 'chip_dragonfly_common_vseq' because it is not registered with the factory. has 30 failures:
0.chip_tl_errors.61557092010146376997762355920792487924551258157364222993516990905353147530194
Line 220, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_tl_errors/latest/run.log
UVM_WARNING @ 0.000000 us: [BDTYP] Cannot create an object of type 'chip_dragonfly_common_vseq' because it is not registered with the factory.
UVM_INFO @ 0.000000 us: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
1.chip_tl_errors.101447640364764418260846717068785733437941653523118263669054342733093546962842
Line 220, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/1.chip_tl_errors/latest/run.log
UVM_WARNING @ 0.000000 us: [BDTYP] Cannot create an object of type 'chip_dragonfly_common_vseq' because it is not registered with the factory.
UVM_INFO @ 0.000000 us: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
... and 28 more failures.
Error-[CNST-CIF] Constraints inconsistency failure has 10 failures:
0.chip_padctrl_attributes.64729452755071654127491320635719572507996770809328911514864364219200385463830
Line 287, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_padctrl_attributes/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 92
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
1.chip_padctrl_attributes.101968592506358911541655219870551532341945369615548368052771390137514486942181
Line 287, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/1.chip_padctrl_attributes/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 92
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
... and 8 more failures.
Job timed out after * minutes has 8 failures:
Test chip_csr_bit_bash has 1 failures.
0.chip_csr_bit_bash.21323019070891058781096967055254614003737299712618028666447050521159922532049
Log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_csr_bit_bash/latest/run.log
Job timed out after 180 minutes
Test chip_csr_aliasing has 1 failures.
0.chip_csr_aliasing.88455352484056779815806854187980141290558586370456325940447790341563813054515
Log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_csr_aliasing/latest/run.log
Job timed out after 180 minutes
Test chip_same_csr_outstanding has 1 failures.
0.chip_same_csr_outstanding.105469228002148967327403647722703821927242311691587691339061370600732388236874
Log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
Job timed out after 120 minutes
Test chip_sw_lc_ctrl_volatile_raw_unlock has 1 failures.
0.chip_sw_lc_ctrl_volatile_raw_unlock.85468579093997759629813993564312971678371219084446615772752800263282692570995
Log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_lc_ctrl_volatile_raw_unlock/latest/run.log
Job timed out after 120 minutes
Test chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz has 1 failures.
0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.37954153592277877334754949540103379301006487947566691006454305466148892479745
Log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest/run.log
Job timed out after 120 minutes
... and 3 more tests.
Offending '((!rstreqs[*]) && (reset_cause != HwReq))' has 5 failures:
Test chip_sw_rstmgr_cpu_info has 1 failures.
0.chip_sw_rstmgr_cpu_info.9777430803740270894846231116673095594271534766331028690611712412849311270423
Line 390, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 412.128000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 412.128000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test chip_sw_clkmgr_off_aes_trans has 1 failures.
0.chip_sw_clkmgr_off_aes_trans.56296852057432298573521975553288793255516847256494745888071415732777811454772
Line 364, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 184.672000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 184.672000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test chip_sw_clkmgr_off_hmac_trans has 1 failures.
0.chip_sw_clkmgr_off_hmac_trans.50172904172940562710537010512513385299998986437182164882509504657028991288757
Line 364, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 184.608000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 184.608000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test chip_sw_clkmgr_off_kmac_trans has 1 failures.
0.chip_sw_clkmgr_off_kmac_trans.95581270868745088457077615054895727714735661204089017622493628407166157822702
Line 364, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 184.544000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 184.544000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test chip_sw_clkmgr_off_acc_trans has 1 failures.
0.chip_sw_clkmgr_off_acc_trans.4271580492422155153539363465278274212033320504119797198965579627790945585169
Line 364, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_clkmgr_off_acc_trans/latest/run.log
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 184.656000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 184.656000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_*_key == get_otp_root_key() (* [*] vs * [*]) Expecting boot stage * key to equal creator root key (UDS) from OTP has 4 failures:
Test chip_sw_keymgr_dpe_key_derivation has 1 failures.
0.chip_sw_keymgr_dpe_key_derivation.66815392905655936787039288173314388828300455818664825422439801746015098428648
Line 384, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log
UVM_ERROR @ 304.344000 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (5445049623764765835057639408035074186647735127492796455270067331523819506225458866483157888615015697909974480901226782392253333182615547150995165005831260 [0x67f6d920aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd3e1a069d17f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
UVM_INFO @ 304.344000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.
0.chip_sw_keymgr_dpe_key_derivation_prod.41415327881421848407163441159870994235524627062007184556271529672036114209293
Line 384, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log
UVM_ERROR @ 304.263000 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (11619560523682953969164245824855835818463540474124999906808341554547195815340996983779304326445251941378342710410680391433966515726201519200321228113271900 [0xdddb3a8faae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35b8d8a7e7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
UVM_INFO @ 304.263000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
0.chip_sw_keymgr_dpe_key_derivation_jitter_en.54728210906346247914755998441993059309259352103971635124196883456407718143443
Line 384, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
UVM_ERROR @ 304.371000 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (4027950734075310721163017584562525982257144639408608925758217671587389021509633601080886977060605875500665302029606325440894713067443163900042861754014812 [0x4ce8368baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd3cabe867a7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
UVM_INFO @ 304.371000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq has 1 failures.
0.chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq.33658357509525747624885785907549870211821463389121307396977108112085869224617
Line 384, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq/latest/run.log
UVM_ERROR @ 3916.378326 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (908646459804490556326724211913134819242120451363176022005673867255735635130020921079119609640604164724750078246551755155920064858318616204178280677727324 [0x11595f12aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd3970fefe37f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
UVM_INFO @ 3916.378326 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job returned non-zero exit code has 3 failures:
Test chip_sw_example_manufacturer has 1 failures.
0.chip_sw_example_manufacturer.42942209797967212394809584627929668925653169750845755043849839226599746627987
Log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log
ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
@@+hooks+manufacturer_test_hooks//:example_test_sim_dv (246fe9) <-- target platform (//toolchain:pavona_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 6.289s, Critical Path: 0.04s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
FAILED:
_run_cmd -> had a non-zero return code of 1.
make: *** [/home/runner/_work/pavona/pavona/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Test chip_sw_kmac_app_rom has 1 failures.
0.chip_sw_kmac_app_rom.94913783245270992789915439442452927731786961662975081262503635355977953806560
Log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
INFO: [build_sw_collateral_for_sim.py:202] cquery_cmd = ./bazelisk.sh cquery labels(data, //sw/device/tests:kmac_app_rom_test_sim_dv) union labels(srcs, //sw/device/tests:kmac_app_rom_test_sim_dv) --ui_event_filters=-info --noshow_progress --//hw/top=dragonfly --//hw/top=dragonfly --output=starlark
---- STDOUT ----
---- STDERR ----
Another command (pid=621341) is running. Waiting for it to complete on the server (server_pid=4137128)...
ERROR: Error doing post analysis query: Evaluation of subquery "labels('data', //sw/device/tests:kmac_app_rom_test_sim_dv)" failed (did you want to use --keep_going?): in 'data' of rule //sw/device/tests:kmac_app_rom_test_sim_dv: configured target of type test_suite does not have attribute 'data'
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/home/runner/_work/pavona/pavona/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Test base_rom_e2e_smoke has 1 failures.
0.base_rom_e2e_smoke.50130537593290015968706585594529702426097180424009706126140946829460903835928
Log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.base_rom_e2e_smoke/latest/run.log
sys.exit(_main())
File "/home/runner/_work/pavona/pavona/util/py/scripts/build_sw_collateral_for_sim.py", line 544, in _main
_deploy_software_collateral(args)
File "/home/runner/_work/pavona/pavona/util/py/scripts/build_sw_collateral_for_sim.py", line 324, in _deploy_software_collateral
image_string = ImageString(image)
File "<string>", line 4, in __init__
File "/home/runner/_work/pavona/pavona/util/py/scripts/build_sw_collateral_for_sim.py", line 256, in __post_init__
assert flag in KNOWN_FLAGS, f"Unknown flag '{flag}' used in sw_image '{self.raw}'"
AssertionError: Unknown flag 'test_in_second_rom' used in sw_image '//sw/device/silicon_creator/rom/e2e:base_rom_e2e_smoke:7:test_in_second_rom'
make: *** [/home/runner/_work/pavona/pavona/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
UVM_ERROR @ * us: (chip_rv_dm_lc_disabled_vseq.sv:73) [chip_rv_dm_lc_disabled_vseq] Check failed dmcontrol == * (* [*] vs * [*]) Writes to dmcontrol must be gated in this LC state has 3 failures:
4.chip_rv_dm_lc_disabled.34480382250339804474054598960498226471181909110747197373690599804002650721653
Line 210, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/4.chip_rv_dm_lc_disabled/latest/run.log
UVM_ERROR @ 124.772953 us: (chip_rv_dm_lc_disabled_vseq.sv:73) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed dmcontrol == 0 (1 [0x1] vs 0 [0x0]) Writes to dmcontrol must be gated in this LC state
UVM_INFO @ 124.772953 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.chip_rv_dm_lc_disabled.33287596253050378889909032439351952489119580918435501722754284618458705731860
Line 210, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/5.chip_rv_dm_lc_disabled/latest/run.log
UVM_ERROR @ 123.810381 us: (chip_rv_dm_lc_disabled_vseq.sv:73) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed dmcontrol == 0 (1 [0x1] vs 0 [0x0]) Writes to dmcontrol must be gated in this LC state
UVM_INFO @ 123.810381 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (cip_base_scoreboard.sv:563) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@41855) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * a_blocked: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:
Test chip_jtag_csr_rw has 1 failures.
0.chip_jtag_csr_rw.32226611348179439433565493975623282708697418620123475433501824474030231277751
Line 5980, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_jtag_csr_rw/latest/run.log
UVM_ERROR @ 117.016000 us: (cip_base_scoreboard.sv:563) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@41855) { a_addr: 'h30480000 a_data: 'ha4c09c92 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h24 a_opcode: 'h1 a_user: 'h248a0 a_blocked: 'h0 d_param: 'h0 d_source: 'h24 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0 trans_blocked: 0
UVM_INFO @ 117.016000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test chip_jtag_mem_access has 1 failures.
0.chip_jtag_mem_access.39192742490432479960875195783554331725060623006060407781689373394948280811134
Line 5980, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_jtag_mem_access/latest/run.log
UVM_ERROR @ 117.009000 us: (cip_base_scoreboard.sv:563) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@41855) { a_addr: 'h30480000 a_data: 'h3daa682d a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h31 a_opcode: 'h0 a_user: 'h26938 a_blocked: 'h0 d_param: 'h0 d_source: 'h31 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0 trans_blocked: 0
UVM_INFO @ 117.009000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:653) [chip_prim_tl_access_vseq] Check failed rsp.d_error == exp_err_rsp (* [*] vs * [*]) unexpected error response for addr: * has 2 failures:
3.chip_prim_tl_access.53953883384876299181416873624197329618606066356340878761075540437901424004290
Line 234, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/3.chip_prim_tl_access/latest/run.log
UVM_ERROR @ 118.023000 us: (cip_base_vseq.sv:653) [uvm_test_top.env.virtual_sequencer.chip_prim_tl_access_vseq] Check failed rsp.d_error == exp_err_rsp (0 [0x0] vs 1 [0x1]) unexpected error response for addr: 0x30140004
UVM_INFO @ 118.023000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.chip_prim_tl_access.28240416673875433196694016164706619587511733480969746209309231245882651340833
Line 234, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/4.chip_prim_tl_access/latest/run.log
UVM_ERROR @ 117.681000 us: (cip_base_vseq.sv:653) [uvm_test_top.env.virtual_sequencer.chip_prim_tl_access_vseq] Check failed rsp.d_error == exp_err_rsp (0 [0x0] vs 1 [0x1]) unexpected error response for addr: 0x30140014
UVM_INFO @ 117.681000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:912) virtual_sequencer [Alert %0s fired unexpectedly.] uart0_fatal_fault has 2 failures:
50.chip_sw_all_escalation_resets.64190731556436011332434113063169399713325336481026250445231853435059641743779
Line 374, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/50.chip_sw_all_escalation_resets/latest/run.log
UVM_ERROR @ 178.204000 us: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] uart0_fatal_fault
UVM_INFO @ 178.204000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
54.chip_sw_all_escalation_resets.96301839611600674247862157155665950571523405264838643675562362330625589722396
Line 369, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/54.chip_sw_all_escalation_resets/latest/run.log
UVM_ERROR @ 178.200000 us: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] uart0_fatal_fault
UVM_INFO @ 178.200000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_spi_passthrough_vseq.sv:101) [chip_sw_spi_passthrough_vseq] Check failed device_rsp_q.size() == * (* [*] vs * [*]) has 1 failures:
0.chip_sw_spi_device_pass_through.68011780825142925794202060265040410128841459216587174977042339355478157430684
Line 371, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_spi_device_pass_through/latest/run.log
UVM_ERROR @ 409.816503 us: (chip_sw_spi_passthrough_vseq.sv:101) [uvm_test_top.env.virtual_sequencer.chip_sw_spi_passthrough_vseq] Check failed device_rsp_q.size() == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 409.816503 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
0.chip_sw_spi_device_pass_through_collision.95740885792861087453379651757410189115769271258731819502016619883271466882634
Line 373, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
UVM_ERROR @ 180.606000 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
UVM_INFO @ 180.606000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' has 1 failures:
0.chip_sw_otp_ctrl_escalation.29632388750568519653625388659593098723224231695322969798885363891170712836358
Line 369, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/run.log
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 176.248000 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 176.248000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:669)] CHECK-fail: alert_info.class_accum_cnt[*] mismatch exp:* obs:* has 1 failures:
0.chip_sw_rstmgr_alert_info.49447469579916223729023039135899178475569267325082639873769851541990175525658
Line 542, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
UVM_ERROR @ 343.949000 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:669)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3 obs:0x1
UVM_INFO @ 343.949000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_soc_proxy_smoke_vseq.sv:36) [chip_env_pkg::\chip_sw_soc_proxy_smoke_vseq::body ] Resets did not complete within required time! has 1 failures:
0.chip_sw_soc_proxy_smoketest.80657483742766447637176317956504591914519779102208090852288660479374892718785
Line 362, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_soc_proxy_smoketest/latest/run.log
UVM_ERROR @ 156.416000 us: (chip_sw_soc_proxy_smoke_vseq.sv:36) [chip_env_pkg::\chip_sw_soc_proxy_smoke_vseq::body ] Resets did not complete within required time!
UVM_INFO @ 156.416000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 1 failures:
0.chip_sw_soc_proxy_external_wakeup.94660735571950386456029313640938734912103318456349265214213143158414517048092
Line 360, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
UVM_ERROR @ 157.584000 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
UVM_INFO @ 157.584000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_gpios_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:105)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 1 failures:
0.chip_sw_soc_proxy_gpios.101242597770534921671709198249226901880360515391499026784502997872908821495285
Line 361, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_soc_proxy_gpios/latest/run.log
UVM_ERROR @ 183.207000 us: (sw_logger_if.sv:526) [soc_proxy_gpios_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:105)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=410009fc MTVAL=00000004
UVM_INFO @ 183.207000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_irq_test_sim_dv(sw/device/tests/aon_timer_irq_test.c:139)] CHECK-fail: Timer took * usec which is not in the range * usec and * usec has 1 failures:
0.chip_sw_aon_timer_irq.74282332433155599020159095924787509076844423972183996898108591489097289596873
Line 361, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log
UVM_ERROR @ 486.578000 us: (sw_logger_if.sv:526) [aon_timer_irq_test_sim_dv(sw/device/tests/aon_timer_irq_test.c:139)] CHECK-fail: Timer took 3272 usec which is not in the range 299 usec and 344 usec
UVM_INFO @ 486.578000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 1 failures:
0.chip_sw_aon_timer_wdog_bite_reset.97442201293690803075579489356334439873113984250231496197910337163035681345187
Line 362, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
UVM_ERROR @ 182.233000 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
UVM_INFO @ 182.233000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_rnd_test_sim_dv(sw/device/tests/rv_core_ibex_rnd_test.c:94)] CHECK-fail: status_value == * has 1 failures:
0.chip_sw_rv_core_ibex_rnd.92251667222948805516612922196005833059444207166817203948720256553576643283323
Line 360, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_rv_core_ibex_rnd/latest/run.log
UVM_ERROR @ 185.568000 us: (sw_logger_if.sv:526) [rv_core_ibex_rnd_test_sim_dv(sw/device/tests/rv_core_ibex_rnd_test.c:94)] CHECK-fail: status_value == 0
UVM_INFO @ 185.568000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
0.chip_sw_rv_core_ibex_nmi_irq.37169090386268254663204881854053496374140382935312571149485396204175355047499
Line 363, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
UVM_ERROR @ 268.863000 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
UVM_INFO @ 268.863000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [dma_abort_sim_dv(sw/device/tests/dma_abort.c:77)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for kSoftwareBarrier == * has 1 failures:
0.chip_sw_dma_abort.37124371421799100550221180491113612351673258431507874175502537722206275128924
Line 366, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_dma_abort/latest/run.log
UVM_ERROR @ 211.736000 us: (sw_logger_if.sv:526) [dma_abort_sim_dv(sw/device/tests/dma_abort.c:77)] CHECK-fail: Timed out after 500 usec (50000 CPU cycles) waiting for kSoftwareBarrier == 1
UVM_INFO @ 211.736000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:693) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 1 failures:
5.chip_sw_rv_core_ibex_lockstep_glitch.79914277832784479485405834671120163727476122386288948995056264250252743884779
Line 360, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/5.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
UVM_FATAL @ 132.048500 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:693) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
UVM_INFO @ 132.048500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected *, got * has 1 failures:
47.chip_sw_all_escalation_resets.85622807078198558124306660078522807470080428052268726621781582993877866988397
Line 375, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/47.chip_sw_all_escalation_resets/latest/run.log
UVM_ERROR @ 176.782000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected 0x30600000, got 0x30600804
UVM_INFO @ 176.782000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---