CHIP_EGRET Simulation Results

Sunday August 02 2026 00:03:30 UTC

GitHub Revision: `0ff052588e`

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
	crypto_lib_hash_stress	crypto_lib_hash_stress				0	0	--
	crypto_lib_ecc_stress	crypto_lib_ecc_stress				0	0	--
	crypto_lib_rsa_key_gen_stress	crypto_lib_rsa_key_gen_stress				0	0	--
	crypto_lib_rsa_stress	crypto_lib_rsa_stress				0	0	--
	crypto_lib_aes_stress	crypto_lib_aes_stress				0	0	--
	crypto_lib_symmetric_keygen	crypto_lib_symmetric_keygen				0	0	--
	crypto_lib_entropy	crypto_lib_entropy				0	0	--
V1	chip_sw_example_tests	chip_sw_example_flash	5.173m	6.543m	3.399ms	1	1	100.00
		chip_sw_example_rom	2.904m	4.055m	2.503ms	1	1	100.00
		chip_sw_example_manufacturer	4.828m	5.539m	2.594ms	1	1	100.00
		chip_sw_example_concurrency	4.329m	4.806m	2.684ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset				0	0	--
V1	csr_rw	chip_csr_rw				0	0	--
V1	csr_bit_bash	chip_csr_bit_bash	5.200s	10.009s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	5.160s	9.042s		0	1	0.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset				0	0	--
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	5.160s	9.042s		0	1	0.00
		chip_csr_rw				0	0	--
V1	xbar_smoke	xbar_smoke	9.800s	25.112s	200.742us	4	4	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	10.665m	11.118m	4.704ms	4	4	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	10.665m	11.118m	4.704ms	4	4	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	10.665m	11.118m	4.704ms	4	4	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	14.136m	14.722m	4.534ms	5	5	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	14.136m	14.722m	4.534ms	5	5	100.00
		chip_sw_uart_tx_rx_idx1	13.970m	14.554m	4.216ms	3	3	100.00
		chip_sw_uart_tx_rx_idx2	13.866m	14.388m	4.925ms	5	5	100.00
		chip_sw_uart_tx_rx_idx3	14.901m	15.497m	4.684ms	5	5	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	1.018h	1.038h	13.748ms	20	20	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	59.446m	1.008h	13.550ms	5	5	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	42.548m	43.354m	14.056ms	3	3	100.00
V1		TOTAL				58	60	96.67
V2	chip_pin_mux	chip_padctrl_attributes	2.898m	3.168m	4.515ms	4	4	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.898m	3.168m	4.515ms	4	4	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	7.449m	7.944m	3.603ms	6	8	75.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	9.859m	10.364m	5.665ms	7	7	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	8.514m	9.064m	4.690ms	3	3	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	35.037m	35.739m	15.362ms	4	4	100.00
		chip_tap_straps_testunlock0	9.282m	9.751m	4.457ms	3	3	100.00
		chip_tap_straps_rma	17.308m	17.833m	7.400ms	3	3	100.00
		chip_tap_straps_prod	16.992m	17.608m	8.688ms	5	5	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	6.462m	6.944m	2.769ms	4	4	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	31.459m	32.339m	9.967ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	18.548m	19.243m	6.017ms	3	3	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	18.548m	19.243m	6.017ms	3	3	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	24.507m	25.169m	8.378ms	3	3	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	32.650m	33.485m	9.727ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	12.810m	13.357m	4.591ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	18.619m	19.407m	5.631ms	1	1	100.00
		chip_sw_acc_ecdsa_op_irq_jitter_en	1.820h	1.847h	17.990ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	5.095m	5.558m	3.416ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	22.973m	23.614m	6.497ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	5.811m	6.258m	3.032ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	30.211m	30.960m	7.700ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	6.031m	6.491m	3.128ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.998m	12.486m	5.262ms	1	1	100.00
		chip_sw_clkmgr_jitter	5.502m	6.041m	2.911ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	7.968m	8.534m	3.819ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	18.841m	19.468m	7.045ms	4	4	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	9.016m	9.495m	5.054ms	3	3	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	6.507m	6.957m	3.014ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	9.016m	9.495m	5.054ms	3	3	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	4.621m	5.234m	2.548ms	1	1	100.00
		chip_sw_aes_smoketest	7.333m	7.926m	3.713ms	1	1	100.00
		chip_sw_aon_timer_smoketest	6.223m	6.743m	2.925ms	1	1	100.00
		chip_sw_clkmgr_smoketest	5.744m	6.243m	2.777ms	1	1	100.00
		chip_sw_csrng_smoketest	6.093m	6.611m	3.434ms	1	1	100.00
		chip_sw_entropy_src_smoketest	28.097m	29.028m	5.974ms	1	1	100.00
		chip_sw_gpio_smoketest	6.709m	7.312m	3.335ms	1	1	100.00
		chip_sw_hmac_smoketest	5.131m	5.609m	2.926ms	1	1	100.00
		chip_sw_kmac_smoketest	7.111m	7.730m	3.232ms	1	1	100.00
		chip_sw_acc_smoketest	40.888m	41.914m	9.624ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	10.132m	10.799m	6.429ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	7.106m	7.695m	5.657ms	1	1	100.00
		chip_sw_rv_plic_smoketest	4.443m	4.975m	2.742ms	1	1	100.00
		chip_sw_rv_timer_smoketest	3.761m	4.257m	2.473ms	1	1	100.00
		chip_sw_rstmgr_smoketest	5.331m	5.810m	2.713ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	3.338m	3.840m	3.063ms	1	1	100.00
		chip_sw_uart_smoketest	4.379m	4.924m	3.016ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	5.567m	6.044m	2.710ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	8.561m	9.280m	3.782ms	0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	5.820h	5.898h	59.927ms	4	4	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	1.536h	1.562h	14.479ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	33.043s	33.043s		0	1	0.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	7.397m	7.994m	3.835ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	6.580m	7.158m	3.325ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap				0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed				0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	2.820s	18.347s		0	30	0.00
V2	tl_d_illegal_access	chip_tl_errors	2.820s	18.347s		0	30	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	5.160s	9.042s		0	1	0.00
		chip_same_csr_outstanding	4.820s	9.031s		0	1	0.00
		chip_csr_hw_reset				0	0	--
		chip_csr_rw				0	0	--
V2	tl_d_partial_access	chip_csr_aliasing	5.160s	9.042s		0	1	0.00
		chip_same_csr_outstanding	4.820s	9.031s		0	1	0.00
		chip_csr_hw_reset				0	0	--
		chip_csr_rw				0	0	--
V2	xbar_base_random_sequence	xbar_random	1.955m	2.215m	2.361ms	9	9	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	7.790s	24.288s	54.618us	100	100	100.00
		xbar_smoke_large_delays	1.108m	1.356m	9.577ms	3	3	100.00
		xbar_smoke_slow_rsp	1.022m	1.275m	5.094ms	3	3	100.00
		xbar_random_zero_delays	1.085m	1.342m	624.678us	8	8	100.00
		xbar_random_large_delays	7.948m	8.231m	57.868ms	100	100	100.00
		xbar_random_slow_rsp	7.079m	7.354m	35.041ms	100	100	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	58.330s	1.260m	1.257ms	100	100	100.00
		xbar_error_and_unmapped_addr	33.180s	48.184s	252.273us	4	4	100.00
V2	xbar_error_cases	xbar_error_random	1.560m	1.810m	2.307ms	3	3	100.00
		xbar_error_and_unmapped_addr	33.180s	48.184s	252.273us	4	4	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	1.810m	2.064m	2.331ms	8	8	100.00
		xbar_access_same_device_slow_rsp	16.788m	17.078m	86.974ms	16	16	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.592m	1.870m	2.672ms	100	100	100.00
V2	xbar_stress_all	xbar_stress_all	9.371m	9.673m	13.384ms	14	14	100.00
		xbar_stress_all_with_error	6.613m	6.879m	10.428ms	5	5	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	15.051m	15.359m	16.251ms	23	23	100.00
		xbar_stress_all_with_reset_error	20.459m	20.789m	11.059ms	9	9	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	1.536h	1.562h	14.479ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	45.441m	46.979m	22.071ms	0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	1.453h	1.476h	15.185ms	1	3	33.33
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	31.036s	31.036s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	21.038s	21.038s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	20.052s	20.052s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	21.062s	21.062s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	22.088s	22.088s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	27.090s	27.090s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	26.099s	26.099s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	1.204m	1.204m		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	26.080s	26.080s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	27.069s	27.069s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	27.056s	27.056s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	26.058s	26.058s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	26.083s	26.083s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	34.130s	34.130s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	2.474m	2.474m		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	1.304m	1.304m		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	26.071s	26.071s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	33.073s	33.073s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	34.090s	34.090s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	1.020m	1.020m		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	26.071s	26.071s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	26.069s	26.069s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	49.134s	49.134s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	53.129s	53.129s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	1.604m	1.604m		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	44.107s	44.107s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	1.002m	1.002m		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	2.055m	2.055m		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	36.065s	36.065s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	1.169m	1.169m		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	1.771m	1.771m		0	1	0.00
		rom_e2e_asm_init_dev	26.051s	26.051s		0	1	0.00
		rom_e2e_asm_init_prod	1.019m	1.019m		0	1	0.00
		rom_e2e_asm_init_prod_end	1.036m	1.036m		0	1	0.00
		rom_e2e_asm_init_rma	35.078s	35.078s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	3.078h	3.144h	27.858ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	3.198h	3.263h	28.418ms	1	3	33.33
		rom_e2e_keymgr_init_rom_ext_invalid_meas	1.807h	1.856h	40.018ms	0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	1.644h	1.692h	15.927ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup				0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup				0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	5.723m	6.227m	2.814ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	5.095m	5.558m	3.416ms	1	1	100.00
V2	chip_sw_aes_multi_block	chip_sw_aes_multi_block				0	0	--
V2	chip_sw_aes_interrupt_encryption	chip_sw_aes_interrupt_encryption				0	0	--
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	6.611m	7.126m	3.599ms	1	1	100.00
V2	chip_sw_aes_prng_reseed	chip_sw_aes_prng_reseed				0	0	--
V2	chip_sw_aes_force_prng_reseed	chip_sw_aes_force_prng_reseed				0	0	--
V2	chip_sw_aes_idle	chip_sw_aes_idle	3.741m	4.307m	2.378ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	51.572m	52.544m	11.944ms	3	3	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	5.230m	5.832m	3.437ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	9.829m	10.437m	5.679ms	1	1	100.00
V2	chip_sw_alert_handler_escalation_nmi_reset	chip_sw_alert_handler_escalation_nmi_reset				0	0	--
V2	chip_sw_alert_handler_escalation_methods	chip_sw_alert_handler_escalation_methods				0	0	--
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	18.753m	19.390m	6.501ms	93	94	98.94
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	15.176m	15.675m	5.064ms	8	8	100.00
		chip_plic_all_irqs_10	14.464m	14.976m	4.623ms	11	11	100.00
		chip_plic_all_irqs_20	13.591m	14.174m	4.632ms	11	11	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	7.118m	7.627m	3.653ms	3	3	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	46.623m	47.557m	13.912ms	6	6	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	9.315m	9.854m	4.606ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	6.333m	6.834m	3.133ms	0	90	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings				0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	35.166m	35.829m	8.031ms	4	4	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	25.847m	26.702m	6.568ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	32.953m	33.701m	8.809ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep				0	1	0.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	7.332m	7.865m	3.442ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	10.132m	10.799m	6.429ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	7.332m	7.865m	3.442ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	12.907m	13.489m	7.502ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	12.907m	13.489m	7.502ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	10.835m	11.410m	8.010ms	5	5	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	14.322m	14.948m	5.916ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_acc_randomness	19.218m	19.871m	6.516ms	1	1	100.00
		chip_sw_aes_idle	3.741m	4.307m	2.378ms	1	1	100.00
		chip_sw_hmac_enc_idle	5.221m	5.706m	3.122ms	1	1	100.00
		chip_sw_kmac_idle	4.471m	4.939m	2.387ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	11.048m	11.617m	5.074ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	10.747m	11.301m	5.427ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	11.539m	12.134m	5.235ms	1	1	100.00
		chip_sw_clkmgr_off_acc_trans	7.498m	7.995m	4.476ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	32.496m	33.247m	11.830ms	4	4	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.673m	13.268m	3.836ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.723m	13.268m	5.346ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	15.172m	15.687m	4.349ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.537m	12.033m	5.057ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.179m	12.701m	4.449ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	12.037m	12.602m	4.093ms	1	1	100.00
		chip_sw_ast_clk_outputs	24.507m	25.169m	8.378ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	11.397m	12.017m	6.117ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	15.172m	15.687m	4.349ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.537m	12.033m	5.057ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	12.810m	13.357m	4.591ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	18.619m	19.407m	5.631ms	1	1	100.00
		chip_sw_acc_ecdsa_op_irq_jitter_en	1.820h	1.847h	17.990ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	5.095m	5.558m	3.416ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	22.973m	23.614m	6.497ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	5.811m	6.258m	3.032ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	30.211m	30.960m	7.700ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	6.031m	6.491m	3.128ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.998m	12.486m	5.262ms	1	1	100.00
		chip_sw_clkmgr_jitter	5.502m	6.041m	2.911ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	4.531m	4.978m	3.289ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	13.017m	13.577m	5.315ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	18.834m	19.484m	6.991ms	1	1	100.00
		chip_sw_acc_ecdsa_op_irq_jitter_en_reduced_freq	1.973h	2.001h	24.589ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	5.663m	6.128m	3.185ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	5.739m	6.212m	2.855ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	28.265m	28.996m	8.688ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	7.067m	7.565m	3.792ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	13.583m	14.141m	5.911ms	3	3	100.00
		chip_sw_flash_init_reduced_freq	47.834m	48.748m	23.542ms	5	5	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	2.466h	2.503h	29.931ms	3	3	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	24.507m	25.169m	8.378ms	3	3	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	12.056m	12.669m	4.414ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	8.437m	8.962m	4.014ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	18.753m	19.390m	6.501ms	93	94	98.94
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	35.166m	35.829m	8.031ms	4	4	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	42.935m	43.674m	8.194ms	3	3	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	8.506m	8.994m	4.431ms	1	1	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	19.216m	19.757m	6.763ms	3	3	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	5.660m	6.208m	3.523ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	2.598h	2.636h	24.772ms	3	3	100.00
		chip_sw_entropy_src_ast_rng_req	4.691m	5.173m	2.702ms	1	1	100.00
		chip_sw_edn_entropy_reqs	21.413m	22.029m	5.862ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	4.691m	5.173m	2.702ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	42.935m	43.674m	8.194ms	3	3	100.00
V2	chip_sw_entropy_src_fuse_en_fw_read	chip_sw_entropy_src_fuse_en_fw_read_test				0	0	--
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	5.604m	6.124m	3.179ms	1	1	100.00
V2	chip_sw_entropy_src_fw_observe_many_contiguous	chip_sw_entropy_src_fw_observe_many_contiguous				0	0	--
V2	chip_sw_entropy_src_fw_extract_and_insert	chip_sw_entropy_src_fw_extract_and_insert				0	0	--
V2	chip_sw_flash_init	chip_sw_flash_init	53.756m	54.713m	22.044ms	5	5	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	18.109m	18.890m	5.680ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	18.619m	19.407m	5.631ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	13.117m	13.843m	4.173ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en	12.810m	13.357m	4.591ms	3	3	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	2.473h	2.505h	44.163ms	10	10	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	53.756m	54.713m	22.044ms	5	5	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	7.591m	8.166m	3.810ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	40.028m	40.875m	9.719ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.636m	5.142m	2.924ms	0	1	0.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	2.473h	2.505h	44.163ms	10	10	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.636m	5.142m	2.924ms	0	1	0.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.636m	5.142m	2.924ms	0	1	0.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	4.636m	5.142m	2.924ms	0	1	0.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.636m	5.142m	2.924ms	0	1	0.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	18.753m	19.390m	6.501ms	93	94	98.94
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	13.185m	13.441m	10.163ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	18.493m	19.206m	4.987ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	11.688m	12.277m	5.124ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	11.688m	12.277m	5.124ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	5.079m	5.556m	2.325ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	5.811m	6.258m	3.032ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	5.221m	5.706m	3.122ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	21.346m	21.979m	5.389ms	1	1	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	14.409m	14.987m	4.614ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	15.829m	16.406m	4.724ms	4	4	100.00
		chip_sw_i2c_host_tx_rx_idx1	14.147m	14.779m	4.355ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	15.091m	15.847m	4.903ms	4	4	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	12.648m	13.324m	4.610ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	40.028m	40.875m	9.719ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	30.211m	30.960m	7.700ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	25.719m	26.416m	6.137ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	51.572m	52.544m	11.944ms	3	3	100.00
V2	chip_sw_keymgr_sideload_acc	chip_sw_keymgr_sideload_acc	1.576h	1.597h	14.200ms	3	3	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	6.259m	6.742m	3.350ms	1	1	100.00
		chip_sw_kmac_mode_kmac	7.644m	8.144m	3.143ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	6.031m	6.491m	3.128ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	40.028m	40.875m	9.719ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	25.057m	25.719m	10.362ms	4	4	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	5.784m	6.292m	3.005ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	35.058m	35.996m	7.198ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	4.471m	4.939m	2.387ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	9.829m	10.437m	5.679ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	35.037m	35.739m	15.362ms	4	4	100.00
		chip_tap_straps_rma	17.308m	17.833m	7.400ms	3	3	100.00
		chip_tap_straps_prod	16.992m	17.608m	8.688ms	5	5	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	4.014m	4.594m	3.500ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	25.057m	25.719m	10.362ms	4	4	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	25.057m	25.719m	10.362ms	4	4	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	25.057m	25.719m	10.362ms	4	4	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	57.245m	58.317m	12.009ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	4.636m	5.142m	2.924ms	0	1	0.00
		chip_sw_flash_rma_unlocked	2.473h	2.505h	44.163ms	10	10	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	7.016m	7.732m	3.234ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	19.825m	20.656m	6.086ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	18.893m	19.571m	6.317ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	14.218m	14.831m	7.069ms	0	1	0.00
		chip_sw_lc_ctrl_transition	25.057m	25.719m	10.362ms	4	4	100.00
		chip_sw_keymgr_key_derivation	40.028m	40.875m	9.719ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	8.732m	9.227m	8.864ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	23.464m	24.136m	8.981ms	1	1	100.00
		chip_prim_tl_access	13.185m	13.441m	10.163ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	11.397m	12.017m	6.117ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.673m	13.268m	3.836ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.723m	13.268m	5.346ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	15.172m	15.687m	4.349ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.537m	12.033m	5.057ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.179m	12.701m	4.449ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	12.037m	12.602m	4.093ms	1	1	100.00
		chip_tap_straps_dev	35.037m	35.739m	15.362ms	4	4	100.00
		chip_tap_straps_rma	17.308m	17.833m	7.400ms	3	3	100.00
		chip_tap_straps_prod	16.992m	17.608m	8.688ms	5	5	100.00
		chip_rv_dm_lc_disabled	1.237m	1.491m	2.451ms	0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	4.854m	5.382m	3.279ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	2.407m	2.825m	3.505ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	2.373m	2.810m	3.085ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	4.716m	5.233m	3.810ms	3	3	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	55.347m	56.523m	27.903ms	1	1	100.00
		chip_rv_dm_lc_disabled	1.237m	1.491m	2.451ms	0	1	0.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	27.666m	28.478m	11.139ms	0	1	0.00
		chip_sw_lc_walkthrough_prod	25.724m	26.457m	9.145ms	0	1	0.00
		chip_sw_lc_walkthrough_prodend	25.188m	25.821m	9.631ms	3	3	100.00
		chip_sw_lc_walkthrough_rma	9.947m	10.449m	5.193ms	0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	55.347m	56.523m	27.903ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.355m	1.772m	2.419ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.786m	2.204m	2.435ms	1	1	100.00
		rom_volatile_raw_unlock	21.029s	21.029s		0	1	0.00
V2	chip_sw_acc_isa	chip_sw_acc_isa				0	0	--
V2	chip_sw_acc_op	chip_sw_acc_ecdsa_op_irq	1.861h	1.887h	16.841ms	3	3	100.00
		chip_sw_acc_ecdsa_op_irq_jitter_en	1.820h	1.847h	17.990ms	1	1	100.00
V2	chip_sw_acc_rnd_entropy	chip_sw_acc_randomness	19.218m	19.871m	6.516ms	1	1	100.00
V2	chip_sw_acc_urnd_entropy	chip_sw_acc_randomness	19.218m	19.871m	6.516ms	1	1	100.00
V2	chip_sw_acc_idle	chip_sw_acc_randomness	19.218m	19.871m	6.516ms	1	1	100.00
V2	chip_sw_acc_mem_scramble	chip_sw_acc_mem_scramble	9.620m	10.158m	3.720ms	1	1	100.00
V2	chip_sw_acc_keymgr	chip_sw_acc_keymgr				0	0	--
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	25.057m	25.719m	10.362ms	4	4	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	53.756m	54.713m	22.044ms	5	5	100.00
		chip_sw_acc_mem_scramble	9.620m	10.158m	3.720ms	1	1	100.00
		chip_sw_keymgr_key_derivation	40.028m	40.875m	9.719ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	14.681m	15.240m	5.002ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.949m	5.463m	2.813ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	53.756m	54.713m	22.044ms	5	5	100.00
		chip_sw_acc_mem_scramble	9.620m	10.158m	3.720ms	1	1	100.00
		chip_sw_keymgr_key_derivation	40.028m	40.875m	9.719ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	14.681m	15.240m	5.002ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.949m	5.463m	2.813ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	25.057m	25.719m	10.362ms	4	4	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	11.682m	12.203m	4.541ms	3	3	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	4.014m	4.594m	3.500ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	7.016m	7.732m	3.234ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	19.825m	20.656m	6.086ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	18.893m	19.571m	6.317ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	14.218m	14.831m	7.069ms	0	1	0.00
		chip_sw_lc_ctrl_transition	25.057m	25.719m	10.362ms	4	4	100.00
		chip_prim_tl_access	13.185m	13.441m	10.163ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	13.185m	13.441m	10.163ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	25.301m	26.045m	6.822ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	12.465m	13.040m	10.218ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	40.849m	41.655m	28.598ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	9.554m	10.133m	7.918ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	10.228m	10.814m	6.971ms	0	1	0.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	16.307m	16.958m	7.588ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	26.075m	26.909m	20.539ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	29.984m	30.772m	13.224ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	12.907m	13.489m	7.502ms	0	1	0.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	29.533m	30.420m	11.110ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	11.073m	11.620m	4.082ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	12.465m	13.040m	10.218ms	3	3	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	10.658m	11.199m	4.729ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	1.346h	1.371h	28.543ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	10.301m	10.814m	7.573ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	11.317m	11.919m	5.593ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	7.472m	7.978m	5.515ms	0	1	0.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	26.863m	27.743m	9.184ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	33.335m	34.209m	11.906ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	46.271m	47.433m	26.020ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	6.325m	6.908m	2.840ms	4	4	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	18.753m	19.390m	6.501ms	93	94	98.94
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	8.732m	9.227m	8.864ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	8.732m	9.227m	8.864ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	33.335m	34.209m	11.906ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	7.472m	7.978m	5.515ms	0	1	0.00
		chip_sw_pwrmgr_wdog_reset	11.073m	11.620m	4.082ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	10.132m	10.799m	6.429ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	11.692m	12.182m	5.245ms	3	3	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	10.901m	11.416m	4.137ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	8.832m	9.446m	4.173ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	46.623m	47.557m	13.912ms	6	6	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	6.029m	6.491m	2.826ms	4	4	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	18.753m	19.390m	6.501ms	93	94	98.94
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	25.847m	26.702m	6.568ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	17.118m	17.689m	4.555ms	3	3	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	18.273m	19.000m	4.972ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	6.330m	6.795m	3.097ms	3	3	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	4.949m	5.463m	2.813ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	10.901m	11.416m	4.137ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	10.901m	11.416m	4.137ms	0	1	0.00
V2	chip_sw_rv_core_ibex_smoke	chip_sw_rv_core_ibex_smoke				0	0	--
V2	chip_sw_rv_core_ibex_epmp_smoke	chip_sw_rv_core_ibex_epmp_smoke				0	0	--
V2	chip_sw_rv_core_ibex_mem_smoke	chip_sw_rv_core_ibex_mem_smoke				0	0	--
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	50.953m	51.764m	18.406ms	8	8	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	30.143m	30.812m	13.943ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	11.692m	12.182m	5.245ms	3	3	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	7.620m	8.147m	2.813ms	0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	54.427m	55.541m	13.629ms	0	1	0.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	17.308m	17.833m	7.400ms	3	3	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	1.237m	1.491m	2.451ms	0	1	0.00
V2	chip_rv_dm_jtag	chip_rv_dm_jtag				0	0	--
V2	chip_rv_dm_dtm	chip_rv_dm_dtm				0	0	--
V2	chip_rv_dm_control_status	chip_rv_dm_control_status				0	0	--
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	15.176m	15.675m	5.064ms	8	8	100.00
		chip_plic_all_irqs_10	14.464m	14.976m	4.623ms	11	11	100.00
		chip_plic_all_irqs_20	13.591m	14.174m	4.632ms	11	11	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	6.811m	7.261m	3.567ms	3	3	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	5.564m	6.041m	3.141ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	1.536h	1.562h	14.479ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	6.478m	6.994m	3.156ms	0	1	0.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision				0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	6.287m	6.812m	3.462ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	6.484m	6.960m	3.495ms	0	3	0.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	14.681m	15.240m	5.002ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.998m	12.486m	5.262ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	13.800m	14.455m	7.231ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	14.183m	14.788m	9.111ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	23.464m	24.136m	8.981ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	18.753m	19.390m	6.501ms	93	94	98.94
		chip_sw_data_integrity_escalation	18.548m	19.243m	6.017ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	26.863m	27.743m	9.184ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	35.230m	36.111m	25.042ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	5.785m	6.310m	3.291ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	8.796m	9.261m	3.980ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	8.685m	9.248m	3.999ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	35.230m	36.111m	25.042ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	35.230m	36.111m	25.042ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	1.517h	1.538h	21.038ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	1.517h	1.538h	21.038ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	12.830m	13.457m	7.261ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup				0	1	0.00
V2	chip_sw_usbdev_mem	chip_sw_usbdev_mem				0	0	--
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	5.359m	5.859m	2.748ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	5.694m	6.276m	3.330ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	11.365m	11.881m	4.345ms	3	3	100.00
V2	chip_sw_usbdev_sof	chip_sw_usbdev_sof				0	0	--
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	14.010m	14.627m	4.017ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	38.548m	39.526m	8.687ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	3.282h	3.330h	31.586ms	3	3	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	1.080h	1.104h	12.634ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	4.494m	4.976m	2.657ms	1	1	100.00
V2		TOTAL				1062	1257	84.49
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	6.603m	7.058m	2.564ms	3	3	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	4.904m	5.377m	2.332ms	3	5	60.00
V2S		TOTAL				6	8	75.00
V3	chip_sw_usb_suspend	chip_sw_usb_suspend				0	0	--
V3	chip_sw_coremark	chip_sw_coremark				0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	15.985m	16.750m	3.779ms	0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	4.415m	6.910m	3.154ms	0	1	0.00
		rom_e2e_jtag_debug_dev	5.024m	7.478m	3.260ms	0	1	0.00
		rom_e2e_jtag_debug_rma	15.071m	17.377m	5.312ms	0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	46.106s	46.106s		0	1	0.00
		rom_e2e_jtag_inject_dev	1.186m	1.186m		0	1	0.00
		rom_e2e_jtag_inject_rma	53.102s	53.102s		0	1	0.00
V3	rom_bootstrap_rma	rom_bootstrap_rma				0	0	--
V3	rom_e2e_weak_straps	rom_e2e_weak_straps				0	0	--
V3	rom_e2e_self_hash	rom_e2e_self_hash	25.037s	25.037s		0	1	0.00
V3	manuf_cp_unlock_raw	manuf_cp_unlock_raw				0	0	--
V3	manuf_scrap	manuf_scrap				0	0	--
V3	manuf_cp_yield_test	manuf_cp_yield_test				0	0	--
V3	manuf_cp_ast_test_execution	manuf_cp_ast_test_execution				0	0	--
V3	manuf_cp_device_info_flash_wr	manuf_cp_device_info_flash_wr				0	0	--
V3	manuf_cp_test_lock	manuf_cp_test_lock				0	0	--
V3	manuf_ft_exit_token	manuf_ft_exit_token				0	0	--
V3	manuf_ft_sku_individualization_preop	manuf_ft_sku_individualization_preop				0	0	--
V3	manuf_ft_sku_individualization	manuf_ft_sku_individualization				0	0	--
V3	manuf_ft_provision_rma_token_and_personalization	manuf_ft_provision_rma_token_and_personalization				0	0	--
V3	manuf_ft_load_transport_image	manuf_ft_load_transport_image				0	0	--
V3	manuf_ft_load_certificates	manuf_ft_load_certificates				0	0	--
V3	manuf_ft_eom	manuf_ft_eom				0	0	--
V3	manuf_rma_entry	manuf_rma_entry				0	0	--
V3	manuf_sram_program_crc_functest	manuf_sram_program_crc_functest				0	0	--
V3	chip_sw_adc_ctrl_normal	chip_sw_adc_ctrl_normal				0	0	--
V3	chip_sw_adc_ctrl_oneshot	chip_sw_adc_ctrl_oneshot				0	0	--
V3	chip_sw_aes_stall_test	chip_sw_aes_stall_test				0	0	--
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	10.240m	10.783m	4.123ms	0	1	0.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	11.200m	11.681m	2.706ms	3	3	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	28.103m	28.771m	5.434ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	48.533m	49.435m	9.926ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	7.707m	8.210m	2.112ms	1	1	100.00
V3	chip_sw_entropy_src_bypass_mode_health_tests	chip_sw_entropy_src_bypass_mode_health_tests				0	0	--
V3	chip_sw_entropy_src_fips_mode_health_tests	chip_sw_entropy_src_fips_mode_health_tests				0	0	--
V3	chip_sw_entropy_src_validation	chip_sw_entropy_src_validation				0	0	--
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	17.764m	18.425m	5.521ms	1	1	100.00
V3	chip_sw_hmac_sha2_stress	chip_sw_hmac_sha2_stress				0	0	--
V3	chip_sw_hmac_stress	chip_sw_hmac_stress				0	0	--
V3	chip_sw_hmac_endianness	chip_sw_hmac_endianness				0	0	--
V3	chip_sw_hmac_secure_wipe	chip_sw_hmac_secure_wipe				0	0	--
V3	chip_sw_hmac_error_conditions	chip_sw_hmac_error_conditions				0	0	--
V3	chip_sw_i2c_speed	chip_sw_i2c_speed				0	0	--
V3	chip_sw_i2c_override	chip_sw_i2c_override				0	0	--
V3	chip_sw_i2c_clockstretching	chip_sw_i2c_clockstretching				0	0	--
V3	chip_sw_i2c_nack	chip_sw_i2c_nack				0	0	--
V3	chip_sw_i2c_repeatedstart	chip_sw_i2c_repeatedstart				0	0	--
V3	chip_sw_keymgr_sideload_kmac_error	chip_sw_keymgr_sideload_kmac_error				0	0	--
V3	chip_sw_keymgr_derive_attestation	chip_sw_keymgr_derive_attestation				0	0	--
V3	chip_sw_keymgr_derive_sealing	chip_sw_keymgr_derive_sealing				0	0	--
V3	chip_sw_kmac_sha3_stress	chip_sw_kmac_sha3_stress				0	0	--
V3	chip_sw_kmac_shake_stress	chip_sw_kmac_shake_stress				0	0	--
V3	chip_sw_kmac_cshake_stress	chip_sw_kmac_cshake_stress				0	0	--
V3	chip_sw_kmac_kmac_stress	chip_sw_kmac_kmac_stress				0	0	--
V3	chip_sw_kmac_kmac_key_sideload	chip_sw_kmac_kmac_key_sideload				0	0	--
V3	chip_sw_kmac_endianness	chip_sw_kmac_endianness				0	0	--
V3	chip_sw_kmac_entropy_stress	chip_sw_kmac_entropy_stress				0	0	--
V3	chip_sw_kmac_error_conditions	chip_sw_kmac_error_conditions				0	0	--
V3	chip_sw_lc_ctrl_kmac_error	chip_sw_lc_ctrl_kmac_error				0	0	--
V3	chip_sw_lc_ctrl_debug_access	chip_sw_lc_ctrl_debug_access				0	0	--
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	5.614m	6.080m	3.275ms	6	6	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	5.844m	6.332m	2.708ms	0	1	0.00
V3	otp_ctrl_calibration	otp_ctrl_calibration				0	0	--
V3	otp_ctrl_partition_access_locked	otp_ctrl_partition_access_locked				0	0	--
V3	otp_ctrl_check_timeout	otp_ctrl_check_timeout				0	0	--
V3	chip_sw_pwm_smoketest	chip_sw_pwm_smoketest				0	0	--
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	11.996m	12.481m	5.525ms	2	3	66.67
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	11.440m	12.001m	5.596ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	33.335m	34.209m	11.906ms	1	1	100.00
V3	chip_sw_rom_ctrl_kmac_error	chip_sw_rom_ctrl_kmac_error				0	0	--
V3	chip_sw_rom_ctrl_digests	chip_sw_rom_ctrl_digests				0	0	--
V3	chip_sw_rv_core_ibex_alerts	chip_sw_rv_core_ibex_alerts				0	0	--
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	4.415m	6.910m	3.154ms	0	1	0.00
		rom_e2e_jtag_debug_dev	5.024m	7.478m	3.260ms	0	1	0.00
		rom_e2e_jtag_debug_rma	15.071m	17.377m	5.312ms	0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	13.816m	14.362m	6.326ms	3	3	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	18.753m	19.390m	6.501ms	93	94	98.94
V3	tick_configuration	chip_sw_rv_timer_systick_test				0	1	0.00
V3	counter_wrap	chip_sw_rv_timer_systick_test				0	1	0.00
V3	chip_sw_spi_device_pass_through_flash_model	chip_sw_spi_device_pass_through_flash_model				0	0	--
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	7.608m	8.129m	3.929ms	3	3	100.00
V3	chip_sw_spi_host_pass_through	chip_sw_spi_host_pass_through				0	0	--
V3	chip_sw_spi_host_configuration	chip_sw_spi_host_configuration				0	0	--
V3	chip_sw_spi_host_events	chip_sw_spi_host_events				0	0	--
V3	chip_sw_sram_memset	chip_sw_sram_memset				0	0	--
V3	chip_sw_sram_readback	chip_sw_sram_readback				0	0	--
V3	chip_sw_sram_subword_access	chip_sw_sram_subword_access				0	0	--
V3	chip_sw_uart_parity	chip_sw_uart_parity				0	0	--
V3	chip_sw_uart_line_loopback	chip_sw_uart_line_loopback				0	0	--
V3	chip_sw_uart_system_loopback	chip_sw_uart_system_loopback				0	0	--
V3	chip_sw_uart_line_break	chip_sw_uart_line_break				0	0	--
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	14.136m	14.722m	4.534ms	5	5	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	1.905h	1.937h	18.841ms	1	1	100.00
V3	chip_sw_usbdev_iso	chip_sw_usbdev_iso				0	0	--
V3	chip_sw_usbdev_mixed	chip_sw_usbdev_mixed				0	0	--
V3	chip_sw_usbdev_suspend_resume	chip_sw_usbdev_suspend_resume				0	0	--
V3	chip_sw_usbdev_aon_wake_reset	chip_sw_usbdev_aon_wake_reset				0	0	--
V3	chip_sw_usbdev_aon_wake_disconnect	chip_sw_usbdev_aon_wake_disconnect				0	0	--
V3		TOTAL				23	38	60.53
	Unmapped tests	chip_sival_flash_info_access	7.391m	7.959m	2.978ms	3	3	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	17.293m	17.974m	6.437ms	3	3	100.00
		chip_sw_otp_ctrl_rot_auth_config	5.450s	36.128s		0	1	0.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	3.832m	4.528m	2.120ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	6.277m	7.066m	3.575ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	9.567m	10.066m	4.705ms	4	4	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	12.014s	12.014s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	4.881m	5.395m	2.823ms	1	1	100.00
		chip_egret_csr_hw_reset	2.820s	18.174s		0	5	0.00
		chip_egret_csr_rw	2.840s	18.369s		0	20	0.00
		chip_egret_csr_bit_bash	2.850s	18.116s		0	5	0.00
		chip_egret_csr_aliasing	2.890s	18.113s		0	5	0.00
		chip_egret_same_csr_outstanding	2.840s	18.315s		0	20	0.00
		chip_egret_csr_mem_rw_with_rand_reset	2.880s	18.359s		0	20	0.00
		TOTAL				1162	1453	79.97

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	21	14	6	28.57
V1	18	15	13	72.22
V2	294	275	203	69.05
V2S	2	2	1	50.00
V3	93	23	10	10.75

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
86.24	94.62	91.51	87.31	37.50	95.78	98.00	98.94

Simulation Wall Clock Time

Target	Elapsed
build	00:07:13
run	30:46:43
cov_merge	30:47:37
cov_report	30:47:52
Total	30:47:52

Failure Buckets

UVM_WARNING @ * us: [BDTYP] Cannot create an object of type 'chip_egret_common_vseq' because it is not registered with the factory. has 105 failures:

Test chip_tl_errors has 30 failures.

0.chip_tl_errors.5438184398050805651319849434627741051093752707103027693991892107658554197164
Line 196, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_WARNING @   0.000000 us: [BDTYP] Cannot create an object of type 'chip_egret_common_vseq' because it is not registered with the factory.
  UVM_INFO @   0.000000 us: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
  #### Factory Configuration (*)
  
  No instance overrides are registered with this factory

1.chip_tl_errors.22462785766246565766419215867000895400154882545988246706667187873852987253332
Line 196, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/1.chip_tl_errors/latest/run.log

  UVM_WARNING @   0.000000 us: [BDTYP] Cannot create an object of type 'chip_egret_common_vseq' because it is not registered with the factory.
  UVM_INFO @   0.000000 us: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
  #### Factory Configuration (*)
  
  No instance overrides are registered with this factory

... and 28 more failures.

Test chip_egret_csr_hw_reset has 5 failures.

0.chip_egret_csr_hw_reset.30882703440080435168037787040617756366886913706738715771130365259097910711640
Line 196, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_egret_csr_hw_reset/latest/run.log

  UVM_WARNING @   0.000000 us: [BDTYP] Cannot create an object of type 'chip_egret_common_vseq' because it is not registered with the factory.
  UVM_INFO @   0.000000 us: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
  #### Factory Configuration (*)
  
  No instance overrides are registered with this factory

1.chip_egret_csr_hw_reset.27099709692757578365671266034416747894049009683286024634805509892686673886897
Line 196, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/1.chip_egret_csr_hw_reset/latest/run.log

  UVM_WARNING @   0.000000 us: [BDTYP] Cannot create an object of type 'chip_egret_common_vseq' because it is not registered with the factory.
  UVM_INFO @   0.000000 us: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
  #### Factory Configuration (*)
  
  No instance overrides are registered with this factory

... and 3 more failures.

Test chip_egret_csr_rw has 20 failures.

0.chip_egret_csr_rw.27511499286464522890635723002314860601423895076658950640958912610626467619414
Line 196, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_egret_csr_rw/latest/run.log

  UVM_WARNING @   0.000000 us: [BDTYP] Cannot create an object of type 'chip_egret_common_vseq' because it is not registered with the factory.
  UVM_INFO @   0.000000 us: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
  #### Factory Configuration (*)
  
  No instance overrides are registered with this factory

1.chip_egret_csr_rw.51757553420620577627805520796004287163240612710413816124151859690222135084717
Line 196, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/1.chip_egret_csr_rw/latest/run.log

  UVM_WARNING @   0.000000 us: [BDTYP] Cannot create an object of type 'chip_egret_common_vseq' because it is not registered with the factory.
  UVM_INFO @   0.000000 us: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
  #### Factory Configuration (*)
  
  No instance overrides are registered with this factory

... and 18 more failures.

Test chip_egret_csr_bit_bash has 5 failures.

0.chip_egret_csr_bit_bash.32447801179068292493057468378037417362619301341991866884055243914566138415308
Line 196, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_egret_csr_bit_bash/latest/run.log

  UVM_WARNING @   0.000000 us: [BDTYP] Cannot create an object of type 'chip_egret_common_vseq' because it is not registered with the factory.
  UVM_INFO @   0.000000 us: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
  #### Factory Configuration (*)
  
  No instance overrides are registered with this factory

1.chip_egret_csr_bit_bash.6267204037446270792612546010534522306013058475141472953219089645165911681607
Line 196, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/1.chip_egret_csr_bit_bash/latest/run.log

  UVM_WARNING @   0.000000 us: [BDTYP] Cannot create an object of type 'chip_egret_common_vseq' because it is not registered with the factory.
  UVM_INFO @   0.000000 us: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
  #### Factory Configuration (*)
  
  No instance overrides are registered with this factory

... and 3 more failures.

Test chip_egret_csr_aliasing has 5 failures.

0.chip_egret_csr_aliasing.55506974193952448274964234156580398324974248192740751938602018295725203916386
Line 196, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_egret_csr_aliasing/latest/run.log

  UVM_WARNING @   0.000000 us: [BDTYP] Cannot create an object of type 'chip_egret_common_vseq' because it is not registered with the factory.
  UVM_INFO @   0.000000 us: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
  #### Factory Configuration (*)
  
  No instance overrides are registered with this factory

1.chip_egret_csr_aliasing.76409127002509479163574913429557633300801478843723209837725721888139684805864
Line 196, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/1.chip_egret_csr_aliasing/latest/run.log

  UVM_WARNING @   0.000000 us: [BDTYP] Cannot create an object of type 'chip_egret_common_vseq' because it is not registered with the factory.
  UVM_INFO @   0.000000 us: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
  #### Factory Configuration (*)
  
  No instance overrides are registered with this factory

... and 3 more failures.

... and 2 more tests.

UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 88 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 88 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.57879934110425395176365220425355692135338779990586787137477080402281194093181
    Line 310, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2601.813576 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2601.813576 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_alert_handler_lpg_sleep_mode_alerts.107778178385112987725036341020487636483188672084757199502144557435028435447198
    Line 310, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/1.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3230.330460 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 3230.330460 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 86 more failures.

Job returned non-zero exit code has 42 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.7865885141785027049241831551252315891207332745936641255739875924666859412951
Log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  ---- STDOUT ----
  
  ---- STDERR ----
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /home/runner/_work/pavona/pavona/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /home/runner/_work/pavona/pavona/sw/device/tests/BUILD
  ERROR: Build did NOT complete successfully
  
  _run_cmd -> had a non-zero return code of 1.
  make: *** [/home/runner/_work/pavona/pavona/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1

Test rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.61692962677928183228014376571336583803122553967950286300937179220228641185838
Log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest/run.log

      File "/home/runner/_work/pavona/pavona/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl
          fail("Bitstream cache not initialized properly.")
  Error in fail: Bitstream cache not initialized properly.
  ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
  ERROR: /home/runner/_work/pavona/pavona/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_egret_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
  ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' failed; build aborted: Analysis failed
  ERROR: Build did NOT complete successfully
  
  _run_cmd -> had a non-zero return code of 1.
  make: *** [/home/runner/_work/pavona/pavona/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1

Test rom_e2e_boot_policy_valid_a_good_b_good_dev has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_good_dev.21760076352534819340819214916716260932689956751698494535963673515731441396390
Log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest/run.log

      File "/home/runner/_work/pavona/pavona/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl
          fail("Bitstream cache not initialized properly.")
  Error in fail: Bitstream cache not initialized properly.
  ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
  ERROR: /home/runner/_work/pavona/pavona/hw/bitstream/hyperdebug/BUILD:22:10: //hw/bitstream/hyperdebug:mmi depends on @@+_repo_rules+bitstreams//:chip_egret_cw310_hyperdebug_mmi in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
  ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' failed; build aborted: Analysis failed
  ERROR: Build did NOT complete successfully
  
  _run_cmd -> had a non-zero return code of 1.
  make: *** [/home/runner/_work/pavona/pavona/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1

Test rom_e2e_boot_policy_valid_a_good_b_good_prod has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_good_prod.104361999435865558207715319055148432277135013704392648429239412134879318447089
Log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_prod/latest/run.log

      File "/home/runner/_work/pavona/pavona/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl
          fail("Bitstream cache not initialized properly.")
  Error in fail: Bitstream cache not initialized properly.
  ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
  ERROR: /home/runner/_work/pavona/pavona/hw/bitstream/hyperdebug/BUILD:22:10: //hw/bitstream/hyperdebug:mmi depends on @@+_repo_rules+bitstreams//:chip_egret_cw310_hyperdebug_mmi in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
  ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' failed; build aborted: Analysis failed
  ERROR: Build did NOT complete successfully
  
  _run_cmd -> had a non-zero return code of 1.
  make: *** [/home/runner/_work/pavona/pavona/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1

Test rom_e2e_boot_policy_valid_a_good_b_good_prod_end has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.102866618527587756692963537142166754456320062782535392592529441483191486439924
Log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end/latest/run.log

      File "/home/runner/_work/pavona/pavona/rules/bitstreams.bzl", line 77, column 13, in _bitstreams_repo_impl
          fail("Bitstream cache not initialized properly.")
  Error in fail: Bitstream cache not initialized properly.
  ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
  ERROR: /home/runner/_work/pavona/pavona/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_egret_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
  ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' failed; build aborted: Analysis failed
  ERROR: Build did NOT complete successfully
  
  _run_cmd -> had a non-zero return code of 1.
  make: *** [/home/runner/_work/pavona/pavona/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1

... and 37 more tests.

Job timed out after * minutes has 8 failures:
- Test chip_sw_inject_scramble_seed has 1 failures.
  - 0.chip_sw_inject_scramble_seed.43924250771749403509374566940427260288959469525513475442532109200733803701937
    Log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_sw_inject_scramble_seed/latest/run.log
```
  Job timed out after 300 minutes
```
- Test chip_sw_exit_test_unlocked_bootstrap has 1 failures.
  - 0.chip_sw_exit_test_unlocked_bootstrap.26081806690310761669120193905118685071883578825879644595854196943912269848616
    Log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_sw_exit_test_unlocked_bootstrap/latest/run.log
```
  Job timed out after 220 minutes
```
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.35688987503876779616707071128717032650408517381442436853225717863416444733763
    Log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  Job timed out after 60 minutes
```
- Test chip_sw_rv_timer_systick_test has 1 failures.
  - 0.chip_sw_rv_timer_systick_test.83823649524924572022144019465715896188417060638324724760784118121499870621028
    Log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job timed out after 120 minutes
```
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.28610211469180190630811275413653388824217941430817685827553027012298760869634
    Log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  Job timed out after 60 minutes
```
- ... and 3 more tests.
Error-[NOA] Null object access has 4 failures:
- Test chip_sw_rv_dm_ndm_reset_req_when_cpu_halted has 1 failures.
  - 0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.115203058857169799773503844386449269517355127411657454128072953943855685539450
    Line 329, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest/run.log
```
  Error-[NOA] Null object access
  src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
    The object at dereference depth 1 is being used before it was
    constructed/allocated.
    Please make sure that the object is allocated before using it.
```
- Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_debug_test_unlocked0.84399485710448923622618886574903604805155826580023938485838942136762224857005
    Line 321, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log
```
  Error-[NOA] Null object access
  src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
    The object at dereference depth 1 is being used before it was
    constructed/allocated.
    Please make sure that the object is allocated before using it.
```
- Test rom_e2e_jtag_debug_dev has 1 failures.
  - 0.rom_e2e_jtag_debug_dev.83221496644211198678489705060408226113201612716591226941035458333137281551180
    Line 321, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log
```
  Error-[NOA] Null object access
  src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
    The object at dereference depth 1 is being used before it was
    constructed/allocated.
    Please make sure that the object is allocated before using it.
```
- Test rom_e2e_jtag_debug_rma has 1 failures.
  - 0.rom_e2e_jtag_debug_rma.23718167045456098904520761391841573232098049044079414254349011681897382181780
    Line 354, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log
```
  Error-[NOA] Null object access
  src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
    The object at dereference depth 1 is being used before it was
    constructed/allocated.
    Please make sure that the object is allocated before using it.
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.86818606168509103578401259075463840026983434525890996667644063007524206124737
    Line 120, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.100717909572396451003379184680093634328325872824789989762295837232076841190649
    Line 120, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.89061087300885142698737860313100288331674582885873911040692722862042897841458
    Line 120, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_test_status_if.sv:85) [tb.u_sim_sram.u_sim_sram_if.u_sw_test_status_if] ==== SW TEST FAILED ==== has 3 failures:
- Test chip_sw_spi_host_tx_rx has 3 failures.
  - 0.chip_sw_spi_host_tx_rx.13491531650401601819196939895407217414333673597858091669656877041704054496
    Line 338, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_sw_spi_host_tx_rx/latest/run.log
```
  UVM_ERROR @ 3181.317364 us: (sw_test_status_if.sv:85) [tb.u_sim_sram.u_sim_sram_if.u_sw_test_status_if] ==== SW TEST FAILED ====
  UVM_INFO @ 3181.317364 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_spi_host_tx_rx.21295485789660413598524490122577426145960005441370765250098849087854549866536
    Line 338, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/1.chip_sw_spi_host_tx_rx/latest/run.log
```
  UVM_ERROR @ 3495.255326 us: (sw_test_status_if.sv:85) [tb.u_sim_sram.u_sim_sram_if.u_sw_test_status_if] ==== SW TEST FAILED ====
  UVM_INFO @ 3495.255326 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected has 3 failures:
- Test chip_sw_lc_walkthrough_dev has 1 failures.
  - 0.chip_sw_lc_walkthrough_dev.32504658001521219592650358306112862675917422163580411206484841309706330593220
    Line 371, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_sw_lc_walkthrough_dev/latest/run.log
```
  UVM_ERROR @ 11138.881634 us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 42 is asserted but not expected
  UVM_INFO @ 11138.881634 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_lc_walkthrough_prod has 1 failures.
  - 0.chip_sw_lc_walkthrough_prod.16888801922704613455143009264969545126739580696530296818037821039592570991894
    Line 371, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_sw_lc_walkthrough_prod/latest/run.log
```
  UVM_ERROR @ 9145.457370 us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 42 is asserted but not expected
  UVM_INFO @ 9145.457370 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_lc_walkthrough_rma has 1 failures.
  - 0.chip_sw_lc_walkthrough_rma.75772214998836886234718369936335719573167593992668264730647302004783813024489
    Line 343, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_sw_lc_walkthrough_rma/latest/run.log
```
  UVM_ERROR @ 5193.211552 us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 42 is asserted but not expected
  UVM_INFO @ 5193.211552 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(rstreqs[*] && (reset_cause == HwReq))' has 3 failures:
- Test chip_sw_pwrmgr_random_sleep_all_reset_reqs has 1 failures.
  - 0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.64300702953135446440551800219398949803263441709508587470917848117404819327079
    Line 317, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest/run.log
```
      Offending '(rstreqs[0] && (reset_cause == HwReq))'
  UVM_ERROR @ 5515.090000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
  UVM_INFO @ 5515.090000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_pwrmgr_deep_sleep_por_reset has 1 failures.
  - 0.chip_sw_pwrmgr_deep_sleep_por_reset.37071787073437822828784532707682832777986228098493988635139059504268866545708
    Line 327, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest/run.log
```
      Offending '(rstreqs[0] && (reset_cause == HwReq))'
  UVM_ERROR @ 6971.420000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
  UVM_INFO @ 6971.420000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.39869061965581185508578023427072232429896859076907412326344525369680933810806
    Line 321, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
      Offending '(rstreqs[1] && (reset_cause == HwReq))'
  UVM_ERROR @ 7501.870000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
  UVM_INFO @ 7501.870000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:139) [chip_sw_power_virus_vseq] Check failed device_rsp_q.size() == * (* [*] vs * [*]) has 3 failures:
- Test chip_sw_power_virus has 3 failures.
  - 0.chip_sw_power_virus.23056689982602551811100579263074462237408012970607735708906887638117531890181
    Line 362, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 4240.660180 us: (chip_sw_power_virus_vseq.sv:139) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed device_rsp_q.size() == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 4240.660180 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_power_virus.35198377726564986487963331551549958523377583404803351629687724795904743878338
    Line 362, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/1.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 3523.528144 us: (chip_sw_power_virus_vseq.sv:139) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed device_rsp_q.size() == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 3523.528144 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = * ns has 2 failures:
- Test rom_e2e_keymgr_init_rom_ext_invalid_meas has 1 failures.
  - 0.rom_e2e_keymgr_init_rom_ext_invalid_meas.96743027147741565822309767552989129235895415730947268957523812395337690733555
    Line 325, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest/run.log
```
  UVM_ERROR @ 40018.377434 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 40000000 ns
  
  UVM_INFO @ 40018.377434 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_keymgr_init_rom_ext_no_meas has 1 failures.
  - 1.rom_e2e_keymgr_init_rom_ext_no_meas.55755282868596353600174970865990960411660329436867951246264574999242087994850
    Line 320, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log
```
  UVM_ERROR @ 40018.530695 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 40000000 ns
  
  UVM_INFO @ 40018.530695 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_FATAL @ * us: (chip_sw_rom_e2e_base_vseq.sv:57) [chip_sw_rom_e2e_shutdown_exception_c_vseq] Timeout occurred when waiting for SRAM initialization; Current sram_ret_init_done = *'*, Timeout value = *ns has 2 failures:

Test rom_e2e_shutdown_exception_c has 2 failures.

1.rom_e2e_shutdown_exception_c.27580907308088970040562633481273284277577922096030324080722724822630543288762
Line 318, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/1.rom_e2e_shutdown_exception_c/latest/run.log

  UVM_FATAL @ 40010.200001 us: (chip_sw_rom_e2e_base_vseq.sv:57) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_shutdown_exception_c_vseq] Timeout occurred when waiting for SRAM initialization; Current sram_ret_init_done = 1'0, Timeout value = 40000000ns
  UVM_INFO @ 40010.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.rom_e2e_shutdown_exception_c.1302898269464947426352395257337435567266819105753644872092613268813810280951
Line 318, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/2.rom_e2e_shutdown_exception_c/latest/run.log

  UVM_FATAL @ 40010.360001 us: (chip_sw_rom_e2e_base_vseq.sv:57) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_shutdown_exception_c_vseq] Timeout occurred when waiting for SRAM initialization; Current sram_ret_init_done = 1'0, Timeout value = 40000000ns
  UVM_INFO @ 40010.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [*] vs *xz [z]) for MIO[*] has 2 failures:
- Test chip_sw_sleep_pin_mio_dio_val has 2 failures.
  - 4.chip_sw_sleep_pin_mio_dio_val.85215440132499695495761253156160074929641922652202370536153663513681094737954
    Line 453, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/4.chip_sw_sleep_pin_mio_dio_val/latest/run.log
```
  UVM_ERROR @ 3021.068000 us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (0x0 [0] vs 0xz [z]) for MIO[30]
  UVM_INFO @ 3021.068000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.chip_sw_sleep_pin_mio_dio_val.79607172122331283482678770686908123555056380359798674480802882234465304166088
    Line 453, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/7.chip_sw_sleep_pin_mio_dio_val/latest/run.log
```
  UVM_ERROR @ 3354.127000 us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (0x0 [0] vs 0xz [z]) for MIO[30]
  UVM_INFO @ 3354.127000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *flash_ctrl*.u_flash.*prim_reg_we_check* has 2 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 2 failures.
  - 25.chip_sw_alert_handler_lpg_sleep_mode_alerts.8958050589206358322042960198467510860500185627895448434529634698672613917839
    Line 303, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/25.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_FATAL @  10.160001 us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *flash_ctrl*.u_flash.*prim_reg_we_check*
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 75.chip_sw_alert_handler_lpg_sleep_mode_alerts.83811282002386074966969265329865148090379903154361713835393709840148179191067
    Line 303, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/75.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_FATAL @  10.280001 us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *flash_ctrl*.u_flash.*prim_reg_we_check*
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_spi_passthrough_vseq.sv:124) [chip_sw_spi_passthrough_vseq] Check failed device_rsp_q.size() == * (* [*] vs * [*]) has 1 failures:
- Test chip_sw_spi_device_pass_through has 1 failures.
  - 0.chip_sw_spi_device_pass_through.18738006221725511171053406872567294853607617897039833300755848123014736933035
    Line 320, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_sw_spi_device_pass_through/latest/run.log
```
  UVM_ERROR @ 3156.194090 us: (chip_sw_spi_passthrough_vseq.sv:124) [uvm_test_top.env.virtual_sequencer.chip_sw_spi_passthrough_vseq] Check failed device_rsp_q.size() == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 3156.194090 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected has 1 failures:
- Test chip_sw_flash_ctrl_lc_rw_en has 1 failures.
  - 0.chip_sw_flash_ctrl_lc_rw_en.101516383250433937317764171599784358568945661628517059797601687044678868509828
    Line 311, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_sw_flash_ctrl_lc_rw_en/latest/run.log
```
  UVM_ERROR @ 2923.584520 us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 35 is asserted but not expected
  UVM_INFO @ 2923.584520 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * has 1 failures:
- Test chip_sw_otp_ctrl_lc_signals_rma has 1 failures.
  - 0.chip_sw_otp_ctrl_lc_signals_rma.41614249297364009022310999597592884846300323457302007805955356342469415516944
    Line 344, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log
```
  UVM_ERROR @ 7068.873752 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to 0x0
  UVM_INFO @ 7068.873752 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' has 1 failures:
- Test chip_sw_otp_ctrl_escalation has 1 failures.
  - 0.chip_sw_otp_ctrl_escalation.111037827677750129021018275013219157524223832523850448435217600152059231810810
    Line 318, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/run.log
```
      Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
  UVM_ERROR @ 2708.094018 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
  UVM_INFO @ 2708.094018 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_otp_ctrl_rot_auth_config has 1 failures.
  - 0.chip_sw_otp_ctrl_rot_auth_config.83034860553708773842425975347654750329914843017587494964007505039638102794494
    Line 284, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_sw_otp_ctrl_rot_auth_config/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.24.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:563) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@114162) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * a_blocked: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.14315169924924297896797863687405360304701489326042063421760760543516610229805
Line 335, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 4136.631947 us: (cip_base_scoreboard.sv:563) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@114162) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h0  a_user: 'h259aa  a_blocked: 'h0  d_param: 'h0  d_source: 'h1  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0 trans_blocked: 0
  UVM_INFO @ 4136.631947 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [sysrst_ctrl_inputs_test_sim_dv(sw/device/tests/sysrst_ctrl_inputs_test.c:114)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for i == *kTestPhase has 1 failures:
- Test chip_sw_sysrst_ctrl_inputs has 1 failures.
  - 0.chip_sw_sysrst_ctrl_inputs.20541399613417209382500510007361627045839206107406643842037554448916014626060
    Line 317, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_sw_sysrst_ctrl_inputs/latest/run.log
```
  UVM_ERROR @ 3291.172140 us: (sw_logger_if.sv:526) [sysrst_ctrl_inputs_test_sim_dv(sw/device/tests/sysrst_ctrl_inputs_test.c:114)] CHECK-fail: Timed out after 10 usec (1000 CPU cycles) waiting for i == *kTestPhase
  UVM_INFO @ 3291.172140 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_egret/sw/autogen/tests/alert_test.c:292)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.38892132675793846854935328235970400682766769210764156554101783342274721893423
    Line 309, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 3437.125111 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_egret/sw/autogen/tests/alert_test.c:292)] CHECK-fail: Expect alert 43!
  UVM_INFO @ 3437.125111 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected has 1 failures:
- Test chip_sw_clkmgr_jitter_frequency has 1 failures.
  - 0.chip_sw_clkmgr_jitter_frequency.103557264249088897411303898399735239196692355887759808186263442763574446635275
    Line 345, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_sw_clkmgr_jitter_frequency/latest/run.log
```
  UVM_ERROR @ 4123.410254 us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 25 is asserted but not expected
  UVM_INFO @ 4123.410254 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:93) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to wakeup from deep sleep. has 1 failures:
- Test chip_sw_rv_dm_access_after_wakeup has 1 failures.
  - 0.chip_sw_rv_dm_access_after_wakeup.4808917897957492098269700906949785281139767039895386314609107336499917286099
    Line 331, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_sw_rv_dm_access_after_wakeup/latest/run.log
```
  UVM_FATAL @ 13629.264700 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:93) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to wakeup from deep sleep.
  UVM_INFO @ 13629.264700 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:649) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:
- Test chip_rv_dm_lc_disabled has 1 failures.
  - 0.chip_rv_dm_lc_disabled.48123871395143835616500507811463689587772998221622019097484056551327163226857
    Line 217, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log
```
  UVM_ERROR @ 2451.411639 us: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x1042c read out mismatch
  UVM_INFO @ 2451.411639 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.91588562121878917005391713980085381502097975487019297582188207362946851203714
    Line 314, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 3834.737500 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH3 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3834.737500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.45554378123680388198534428045908955667712599460462839652073378993734614706815
    Line 320, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3324.923000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH3 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3324.923000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:80)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = * has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.41457022882345389837072729237765535856085740798577441170477292408476758881433
    Line 329, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 9727.097424 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:80)] CHECK-fail: Only adc_ctrl IRQ 4294967271 expected to fire. Actual IRQ state = 1
  UVM_INFO @ 9727.097424 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_rom_e2e_shutdown_output_vseq.sv:23) [chip_sw_rom_e2e_shutdown_output_vseq] wait timeout occurred! has 1 failures:
- Test rom_e2e_shutdown_output has 1 failures.
  - 0.rom_e2e_shutdown_output.11421082662387683033477156518971575364546514519354356931435497321393329819955
    Line 331, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.rom_e2e_shutdown_output/latest/run.log
```
  UVM_FATAL @ 22070.614401 us: (chip_sw_rom_e2e_shutdown_output_vseq.sv:23) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_shutdown_output_vseq] wait timeout occurred!
  UVM_INFO @ 22070.614401 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '$stable(key_data_i)' has 1 failures:
- Test rom_keymgr_functest has 1 failures.
  - 0.rom_keymgr_functest.49826893609776180219301860893411815166977835198235689858870672676726383068470
    Line 329, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.rom_keymgr_functest/latest/run.log
```
      Offending '$stable(key_data_i)'
  UVM_ERROR @ 3781.634636 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
  UVM_INFO @ 3781.634636 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_sensor_ctrl_deep_sleep_wake_up_sim_dv(sw/device/tests/pwrmgr_sensor_ctrl_deep_sleep_wake_up.c:120)] CHECK-STATUS-fail: * has 1 failures:
- Test chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up has 1 failures.
  - 2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.87575438075312571805887783067338744970027115870495290987846102899364365103732
    Line 318, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest/run.log
```
  UVM_ERROR @ 5568.596539 us: (sw_logger_if.sv:526) [pwrmgr_sensor_ctrl_deep_sleep_wake_up_sim_dv(sw/device/tests/pwrmgr_sensor_ctrl_deep_sleep_wake_up.c:120)] CHECK-STATUS-fail: 0x00000680
  UVM_INFO @ 5568.596539 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(outstanding_reqs_d <= MAX_REQS)' has 1 failures:
- Test chip_sw_rv_core_ibex_lockstep_glitch has 1 failures.
  - 2.chip_sw_rv_core_ibex_lockstep_glitch.45783063673801476087215307026526607176414942891445654616593397972114537165705
    Line 321, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/2.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
```
      Offending '(outstanding_reqs_d <= MAX_REQS)'
  UVM_ERROR @ 2801.453125 us: (tlul_adapter_host.sv:188) [ASSERT FAILED] DontExceeedMaxReqs
  UVM_INFO @ 2801.453125 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_no_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns * has 1 failures:
- Test rom_e2e_keymgr_init_rom_ext_no_meas has 1 failures.
  - 2.rom_e2e_keymgr_init_rom_ext_no_meas.38909558038063875852354754249787375718190432384365262335155171114199988009901
    Line 321, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/2.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log
```
  UVM_ERROR @ 15623.893700 us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_no_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns 13
  UVM_INFO @ 15623.893700 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:738) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 1 failures:
- Test chip_sw_rv_core_ibex_lockstep_glitch has 1 failures.
  - 4.chip_sw_rv_core_ibex_lockstep_glitch.101498820968515125213616565514488219635574162226087322207623158344791065464676
    Line 325, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/4.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
```
  UVM_FATAL @ 2217.227920 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:738) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
  UVM_INFO @ 2217.227920 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:912) virtual_sequencer [Alert %0s fired unexpectedly.] usbdev_fatal_fault has 1 failures:
- Test chip_sw_all_escalation_resets has 1 failures.
  - 81.chip_sw_all_escalation_resets.42536830409694757886498640733651863482905879122084891485639448006770898079532
    Line 318, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/81.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 2684.985106 us: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] usbdev_fatal_fault
  UVM_INFO @ 2684.985106 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```