CLKMGR/DRAGONFLY Simulation Results

Sunday August 02 2026 00:03:30 UTC

GitHub Revision: 0ff052588e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	0.660s	5.052s	26.211us	1	1	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	0.670s	5.126s	25.271us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	1.130s	7.195s	112.590us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	3.470s	11.163s	338.507us	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	1.740s	8.136s	204.262us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	2.250s	8.186s	297.513us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	1.130s	7.195s	112.590us	20	20	100.00
		clkmgr_csr_aliasing	1.740s	8.136s	204.262us	5	5	100.00
V1		TOTAL				56	56	100.00
V2	peri_enables	clkmgr_peri	1.140s	5.049s	114.047us	1	1	100.00
V2	trans_enables	clkmgr_trans	1.490s	7.067s	153.806us	1	1	100.00
V2	clk_status	clkmgr_clk_status	0.750s	6.065s	50.631us	3	3	100.00
V2	jitter	clkmgr_smoke	0.660s	5.052s	26.211us	1	1	100.00
V2	frequency	clkmgr_frequency	1.080s	5.052s	83.096us	1	1	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	0.610s	5.048s	16.301us	1	1	100.00
V2	frequency_overflow	clkmgr_frequency	1.080s	5.052s	83.096us	1	1	100.00
V2	stress_all	clkmgr_stress_all	2.500s	7.072s	314.873us	1	1	100.00
V2	intr_test	clkmgr_intr_test				0	0	--
V2	alert_test	clkmgr_alert_test	1.080s	8.082s	92.407us	3	3	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	3.050s	9.121s	373.334us	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	3.050s	9.121s	373.334us	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	0.670s	5.126s	25.271us	5	5	100.00
		clkmgr_csr_rw	1.130s	7.195s	112.590us	20	20	100.00
		clkmgr_csr_aliasing	1.740s	8.136s	204.262us	5	5	100.00
		clkmgr_same_csr_outstanding	1.820s	10.199s	242.936us	20	20	100.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	0.670s	5.126s	25.271us	5	5	100.00
		clkmgr_csr_rw	1.130s	7.195s	112.590us	20	20	100.00
		clkmgr_csr_aliasing	1.740s	8.136s	204.262us	5	5	100.00
		clkmgr_same_csr_outstanding	1.820s	10.199s	242.936us	20	20	100.00
V2		TOTAL				51	51	100.00
V2S	tl_intg_err	clkmgr_sec_cm	3.660s	9.113s	497.528us	4	4	100.00
		clkmgr_tl_intg_err	2.720s	8.118s	337.288us	4	4	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	1.230s	5.078s	115.784us	4	4	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	1.230s	5.078s	115.784us	4	4	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	1.230s	5.078s	115.784us	4	4	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	1.230s	5.078s	115.784us	4	4	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	1.970s	6.087s	225.050us	3	3	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	2.720s	8.118s	337.288us	4	4	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	1.080s	5.052s	83.096us	1	1	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	0.610s	5.048s	16.301us	1	1	100.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	1.230s	5.078s	115.784us	4	4	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	1.280s	7.074s	124.195us	3	3	100.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	1.130s	7.195s	112.590us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	3.660s	9.113s	497.528us	4	4	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	1.130s	7.195s	112.590us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	1.130s	7.195s	112.590us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	3.660s	9.113s	497.528us	4	4	100.00
V2S		TOTAL				18	18	100.00
V3	regwen	clkmgr_regwen	1.070s	8.081s	50.864us	4	4	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	55.020s	58.843s	4.655ms	3	4	75.00
V3		TOTAL				7	8	87.50
		TOTAL				132	133	99.25

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	10	9	9	90.00
V2S	5	5	5	100.00
V3	2	2	1	50.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.37	98.53	94.51	100.00	100.00	98.23	96.07	87.26

Simulation Wall Clock Time

Target	Elapsed
build	00:07:13
run	30:46:43
cov_merge	30:47:37
cov_report	30:47:52
Total	30:47:52

Failure Buckets

• UVM_ERROR (clkmgr_frequency_timeout_vseq.sv:113) [clkmgr_frequency_timeout_vseq] Check failed current_alert_count != prior_alert_count (* [*] vs * [*]) expected some alerts to fire has 1 failures:
  • Test clkmgr_stress_all_with_rand_reset has 1 failures.

    • 1.clkmgr_stress_all_with_rand_reset.10561570107513530210078894005217944026763586391806129939817565386802495863626
      Line 117, in log /home/runner/_work/pavona/pavona/scratch/main/clkmgr_top_dragonfly-sim-vcs/1.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  63389877 ps: (clkmgr_frequency_timeout_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Check failed current_alert_count != prior_alert_count (38 [0x26] vs 38 [0x26]) expected some alerts to fire
        UVM_INFO @  63389877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---