CLKMGR/EGRET Simulation Results

Sunday August 02 2026 00:03:30 UTC

GitHub Revision: 0ff052588e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	0.600s	5.100s	16.025us	1	1	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	0.620s	6.073s	53.359us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	0.810s	8.085s	179.742us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	3.300s	7.188s	400.360us	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	1.220s	5.115s	227.754us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	1.640s	7.172s	723.433us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	0.810s	8.085s	179.742us	20	20	100.00
		clkmgr_csr_aliasing	1.220s	5.115s	227.754us	5	5	100.00
V1		TOTAL				56	56	100.00
V2	peri_enables	clkmgr_peri	0.740s	7.114s	115.782us	1	1	100.00
V2	trans_enables	clkmgr_trans	0.800s	5.067s	109.557us	1	1	100.00
V2	extclk	clkmgr_extclk	0.660s	9.165s	15.722us	1	1	100.00
V2	clk_status	clkmgr_clk_status	0.620s	7.095s	16.867us	3	3	100.00
V2	jitter	clkmgr_smoke	0.600s	5.100s	16.025us	1	1	100.00
V2	frequency	clkmgr_frequency	4.280s	13.207s	1.934ms	1	1	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	4.540s	11.190s	2.206ms	1	1	100.00
V2	frequency_overflow	clkmgr_frequency	4.280s	13.207s	1.934ms	1	1	100.00
V2	stress_all	clkmgr_stress_all	19.340s	25.291s	5.284ms	5	5	100.00
V2	intr_test	clkmgr_intr_test				0	0	--
V2	alert_test	clkmgr_alert_test	0.720s	7.084s	73.051us	3	3	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	2.330s	10.226s	466.898us	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	2.330s	10.226s	466.898us	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	0.620s	6.073s	53.359us	5	5	100.00
		clkmgr_csr_rw	0.810s	8.085s	179.742us	20	20	100.00
		clkmgr_csr_aliasing	1.220s	5.115s	227.754us	5	5	100.00
		clkmgr_same_csr_outstanding	1.090s	8.108s	301.940us	20	20	100.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	0.620s	6.073s	53.359us	5	5	100.00
		clkmgr_csr_rw	0.810s	8.085s	179.742us	20	20	100.00
		clkmgr_csr_aliasing	1.220s	5.115s	227.754us	5	5	100.00
		clkmgr_same_csr_outstanding	1.090s	8.108s	301.940us	20	20	100.00
V2		TOTAL				56	56	100.00
V2S	tl_intg_err	clkmgr_sec_cm	2.130s	7.078s	625.848us	3	3	100.00
		clkmgr_tl_intg_err	1.940s	7.191s	377.690us	8	8	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	1.550s	7.081s	372.857us	4	4	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	1.550s	7.081s	372.857us	4	4	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	1.550s	7.081s	372.857us	4	4	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	1.550s	7.081s	372.857us	4	4	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	4.390s	9.209s	2.380ms	5	5	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	1.940s	7.191s	377.690us	8	8	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	4.280s	13.207s	1.934ms	1	1	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	4.540s	11.190s	2.206ms	1	1	100.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	1.550s	7.081s	372.857us	4	4	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	0.780s	8.122s	95.946us	3	3	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	clkmgr_lc_ctrl_intersig_mubi	0.740s	8.123s	23.393us	1	1	100.00
V2S	sec_cm_lc_ctrl_clk_handshake_intersig_mubi	clkmgr_lc_clk_byp_req_intersig_mubi	0.730s	9.135s	33.141us	1	1	100.00
V2S	sec_cm_clk_handshake_intersig_mubi	clkmgr_clk_handshake_intersig_mubi	0.820s	7.093s	35.791us	5	5	100.00
V2S	sec_cm_div_intersig_mubi	clkmgr_div_intersig_mubi	0.690s	5.093s	21.723us	1	1	100.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	0.810s	8.085s	179.742us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	2.130s	7.078s	625.848us	3	3	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	0.810s	8.085s	179.742us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	0.810s	8.085s	179.742us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	2.130s	7.078s	625.848us	3	3	100.00
V2S		TOTAL				31	31	100.00
V3	regwen	clkmgr_regwen	3.700s	12.147s	1.202ms	5	5	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	44.550s	48.411s	8.420ms	3	3	100.00
V3		TOTAL				8	8	100.00
		TOTAL				151	151	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	10	10	90.91
V2S	9	9	9	100.00
V3	2	2	2	100.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.01	99.34	96.26	100.00	100.00	99.17	96.47	87.82

Simulation Wall Clock Time

Target	Elapsed
build	00:07:13
run	30:46:43
cov_merge	30:47:37
cov_report	30:47:52
Total	30:47:52