CSRNG Simulation Results

Sunday August 02 2026 00:03:30 UTC

GitHub Revision: 0ff052588e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	2.230s	35.096s	116.726us	5	5	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	1.430s	7.055s	36.781us	5	5	100.00
V1	csr_rw	csrng_csr_rw	1.470s	6.136s	35.818us	3	3	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	27.380s	31.279s	2.170ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	4.000s	9.079s	180.466us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	3.460s	10.092s	177.336us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	1.470s	6.136s	35.818us	3	3	100.00
		csrng_csr_aliasing	4.000s	9.079s	180.466us	5	5	100.00
V1		TOTAL				43	43	100.00
V2	interrupts	csrng_intr	11.460s	1.218m	649.225us	24	24	100.00
V2	alerts	csrng_alert	16.770s	1.168m	1.146ms	18	18	100.00
V2	err	csrng_err	1.830s	1.201m	32.443us	66	66	100.00
V2	cmds	csrng_cmds	5.123m	5.394m	31.568ms	11	11	100.00
V2	life cycle	csrng_cmds	5.123m	5.394m	31.568ms	11	11	100.00
V2	stress_all	csrng_stress_all	35.055m	35.791m	176.084ms	7	7	100.00
V2	intr_test	csrng_intr_test	3.010s	10.093s	219.298us	50	50	100.00
V2	alert_test	csrng_alert_test	1.360s	35.097s	27.506us	3	3	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	9.170s	13.113s	682.045us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	9.170s	13.113s	682.045us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	1.430s	7.055s	36.781us	5	5	100.00
		csrng_csr_rw	1.470s	6.136s	35.818us	3	3	100.00
		csrng_csr_aliasing	4.000s	9.079s	180.466us	5	5	100.00
		csrng_same_csr_outstanding	4.040s	12.105s	309.848us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	1.430s	7.055s	36.781us	5	5	100.00
		csrng_csr_rw	1.470s	6.136s	35.818us	3	3	100.00
		csrng_csr_aliasing	4.000s	9.079s	180.466us	5	5	100.00
		csrng_same_csr_outstanding	4.040s	12.105s	309.848us	20	20	100.00
V2		TOTAL				219	219	100.00
V2S	tl_intg_err	csrng_sec_cm	3.010s	32.093s	187.565us	3	3	100.00
		csrng_tl_intg_err	5.030s	11.088s	437.281us	6	6	100.00
V2S	sec_cm_config_regwen	csrng_regwen	1.250s	30.095s	12.765us	3	3	100.00
		csrng_csr_rw	1.470s	6.136s	35.818us	3	3	100.00
V2S	sec_cm_config_mubi	csrng_alert	16.770s	1.168m	1.146ms	18	18	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	35.055m	35.791m	176.084ms	7	7	100.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	11.460s	1.218m	649.225us	24	24	100.00
		csrng_err	1.830s	1.201m	32.443us	66	66	100.00
		csrng_sec_cm	3.010s	32.093s	187.565us	3	3	100.00
V2S	sec_cm_updrsp_fsm_sparse	csrng_intr	11.460s	1.218m	649.225us	24	24	100.00
		csrng_err	1.830s	1.201m	32.443us	66	66	100.00
		csrng_sec_cm	3.010s	32.093s	187.565us	3	3	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	11.460s	1.218m	649.225us	24	24	100.00
		csrng_err	1.830s	1.201m	32.443us	66	66	100.00
		csrng_sec_cm	3.010s	32.093s	187.565us	3	3	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	11.460s	1.218m	649.225us	24	24	100.00
		csrng_err	1.830s	1.201m	32.443us	66	66	100.00
		csrng_sec_cm	3.010s	32.093s	187.565us	3	3	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	11.460s	1.218m	649.225us	24	24	100.00
		csrng_err	1.830s	1.201m	32.443us	66	66	100.00
		csrng_sec_cm	3.010s	32.093s	187.565us	3	3	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	11.460s	1.218m	649.225us	24	24	100.00
		csrng_err	1.830s	1.201m	32.443us	66	66	100.00
		csrng_sec_cm	3.010s	32.093s	187.565us	3	3	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	11.460s	1.218m	649.225us	24	24	100.00
		csrng_err	1.830s	1.201m	32.443us	66	66	100.00
		csrng_sec_cm	3.010s	32.093s	187.565us	3	3	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	11.460s	1.218m	649.225us	24	24	100.00
		csrng_err	1.830s	1.201m	32.443us	66	66	100.00
		csrng_sec_cm	3.010s	32.093s	187.565us	3	3	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	16.770s	1.168m	1.146ms	18	18	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	11.460s	1.218m	649.225us	24	24	100.00
		csrng_err	1.830s	1.201m	32.443us	66	66	100.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	35.055m	35.791m	176.084ms	7	7	100.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	16.770s	1.168m	1.146ms	18	18	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	5.030s	11.088s	437.281us	6	6	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	11.460s	1.218m	649.225us	24	24	100.00
		csrng_err	1.830s	1.201m	32.443us	66	66	100.00
		csrng_sec_cm	3.010s	32.093s	187.565us	3	3	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	11.460s	1.218m	649.225us	24	24	100.00
		csrng_err	1.830s	1.201m	32.443us	66	66	100.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	11.460s	1.218m	649.225us	24	24	100.00
		csrng_err	1.830s	1.201m	32.443us	66	66	100.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	11.460s	1.218m	649.225us	24	24	100.00
		csrng_err	1.830s	1.201m	32.443us	66	66	100.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	11.460s	1.218m	649.225us	24	24	100.00
		csrng_err	1.830s	1.201m	32.443us	66	66	100.00
		csrng_sec_cm	3.010s	32.093s	187.565us	3	3	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	11.460s	1.218m	649.225us	24	24	100.00
		csrng_err	1.830s	1.201m	32.443us	66	66	100.00
V2S		TOTAL				12	12	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	4.130m	4.448m	14.290ms	3	3	100.00
V3		TOTAL				3	3	100.00
		TOTAL				277	277	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	9	100.00
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.35	98.97	94.49	99.19	75.19	98.39	95.47	91.73

Simulation Wall Clock Time

Target	Elapsed
build	00:07:13
run	30:46:43
cov_merge	30:47:37
cov_report	30:47:52
Total	30:47:52