DMA Simulation Results

Sunday August 02 2026 00:03:30 UTC

GitHub Revision: 0ff052588e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	5.720s	4.120m	325.579us	25	25	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	6.580s	4.137m	1.637ms	25	25	100.00
V1	dma_generic_smoke	dma_generic_smoke	6.750s	3.903m	874.733us	50	50	100.00
V1	csr_hw_reset	dma_csr_hw_reset	1.170s	45.070s	20.705us	5	5	100.00
V1	csr_rw	dma_csr_rw	1.150s	30.069s	81.915us	3	3	100.00
V1	csr_bit_bash	dma_csr_bit_bash	7.770s	52.096s	592.372us	5	5	100.00
V1	csr_aliasing	dma_csr_aliasing	4.750s	47.069s	428.918us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	1.350s	42.069s	84.755us	3	3	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	1.150s	30.069s	81.915us	3	3	100.00
		dma_csr_aliasing	4.750s	47.069s	428.918us	5	5	100.00
V1		TOTAL				121	121	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	3.222m	4.441m	9.752ms	3	3	100.00
V2	dma_memory_tl_error	dma_memory_stress	13.831m	14.833m	75.295ms	10	11	90.91
V2	dma_handshake_tl_error	dma_handshake_stress	36.608m	36.787m	245.971ms	11	13	84.62
V2	dma_handshake_stress	dma_handshake_stress	36.608m	36.787m	245.971ms	11	13	84.62
V2	dma_memory_stress	dma_memory_stress	13.831m	14.833m	75.295ms	10	11	90.91
V2	dma_generic_stress	dma_generic_stress	36.466m	39.069m	254.506ms	14	14	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	36.608m	36.787m	245.971ms	11	13	84.62
V2	dma_abort	dma_abort	11.580s	1.769m	22.093ms	5	5	100.00
V2	dma_stress_all	dma_stress_all	2.714m	5.438m	12.636ms	7	8	87.50
V2	alert_test	dma_alert_test	0.960s	1.753m	19.575us	3	3	100.00
V2	intr_test	dma_intr_test	0.980s	45.070s	33.805us	5	5	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	2.250s	48.071s	269.198us	6	6	100.00
V2	tl_d_illegal_access	dma_tl_errors	2.250s	48.071s	269.198us	6	6	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	1.170s	45.070s	20.705us	5	5	100.00
		dma_csr_rw	1.150s	30.069s	81.915us	3	3	100.00
		dma_csr_aliasing	4.750s	47.069s	428.918us	5	5	100.00
		dma_same_csr_outstanding	2.000s	48.071s	123.747us	20	20	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	1.170s	45.070s	20.705us	5	5	100.00
		dma_csr_rw	1.150s	30.069s	81.915us	3	3	100.00
		dma_csr_aliasing	4.750s	47.069s	428.918us	5	5	100.00
		dma_same_csr_outstanding	2.000s	48.071s	123.747us	20	20	100.00
V2		TOTAL				84	88	95.45
V2S	dma_illegal_addr_range	dma_mem_enabled	23.860s	4.170m	105.997us	17	17	100.00
		dma_generic_stress	36.466m	39.069m	254.506ms	14	14	100.00
		dma_handshake_stress	36.608m	36.787m	245.971ms	11	13	84.62
V2S	dma_config_lock	dma_config_lock	5.840s	1.019m	1.239ms	3	3	100.00
V2S	tl_intg_err	dma_tl_intg_err	2.440s	31.067s	657.036us	3	3	100.00
		dma_sec_cm	0.980s	3.536m	38.811us	5	5	100.00
V2S		TOTAL				28	28	100.00
V3		TOTAL				0	0	--
	Unmapped tests	dma_short_transfer	2.300m	5.387m	7.281ms	13	13	100.00
		dma_longer_transfer	17.350s	1.735m	2.550ms	5	5	100.00
		dma_stress_all_with_rand_reset	10.640s	24.073s	2.272ms	0	1	0.00
		TOTAL				251	256	98.05

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	3	3	2	66.67
V1	8	8	8	100.00
V2	10	10	7	70.00
V2S	4	4	4	100.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
91.30	97.36	95.82	80.25	87.72	95.98	95.86	86.11

Simulation Wall Clock Time

Target	Elapsed
build	00:07:13
run	30:46:43
cov_merge	30:47:37
cov_report	30:47:52
Total	30:47:52

Failure Buckets

• UVM_ERROR @ *ps: (dma_generic_vseq.sv:36) [dma_handshake_stress_vseq] Check failed (dma_config.is_valid_config) has 2 failures:

  • Test dma_handshake_stress has 2 failures.

    • 11.dma_handshake_stress.39508127228992215702836761291353456388796392372692397356701312872838681557125
      Line 285, in log /home/runner/_work/pavona/pavona/scratch/main/dma-sim-vcs/11.dma_handshake_stress/latest/run.log

        UVM_ERROR @ 135148871839ps: (dma_generic_vseq.sv:36) [uvm_test_top.env.virtual_sequencer.dma_handshake_stress_vseq] Check failed (dma_config.is_valid_config)
        UVM_INFO @ 135148871839ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 12.dma_handshake_stress.68310197547211308198033940704280742122433774116996638473750154094637516159497
      Line 519, in log /home/runner/_work/pavona/pavona/scratch/main/dma-sim-vcs/12.dma_handshake_stress/latest/run.log

        UVM_ERROR @ 604990362938ps: (dma_generic_vseq.sv:36) [uvm_test_top.env.virtual_sequencer.dma_handshake_stress_vseq] Check failed (dma_config.is_valid_config)
        UVM_INFO @ 604990362938ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ *ps: (cip_base_vseq.sv:1237) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test dma_stress_all_with_rand_reset has 1 failures.

    • 0.dma_stress_all_with_rand_reset.15476719953668348088871877709356015959248917529629897436804206841305224633494
      Line 104, in log /home/runner/_work/pavona/pavona/scratch/main/dma-sim-vcs/0.dma_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2271773418ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10010 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2271773418ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ *ps: (dma_generic_vseq.sv:36) [dma_stress_all_vseq] Check failed (dma_config.is_valid_config) has 1 failures:

  • Test dma_stress_all has 1 failures.

    • 6.dma_stress_all.30339768915122227594687809009358979531849182708277274988838544691164294897149
      Line 378, in log /home/runner/_work/pavona/pavona/scratch/main/dma-sim-vcs/6.dma_stress_all/latest/run.log

        UVM_ERROR @ 9249417349ps: (dma_generic_vseq.sv:36) [uvm_test_top.env.virtual_sequencer.dma_stress_all_vseq] Check failed (dma_config.is_valid_config)
        UVM_INFO @ 9249417349ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ *ps: (dma_generic_vseq.sv:36) [dma_memory_stress_vseq] Check failed (dma_config.is_valid_config) has 1 failures:

  • Test dma_memory_stress has 1 failures.

    • 9.dma_memory_stress.45459761666306534716224471509559529116128714677625644505379195434856409930334
      Line 161, in log /home/runner/_work/pavona/pavona/scratch/main/dma-sim-vcs/9.dma_memory_stress/latest/run.log

        UVM_ERROR @ 53672577261ps: (dma_generic_vseq.sv:36) [uvm_test_top.env.virtual_sequencer.dma_memory_stress_vseq] Check failed (dma_config.is_valid_config)
        UVM_INFO @ 53672577261ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---