EDN/EDN0 Simulation Results

Sunday August 02 2026 00:03:30 UTC

GitHub Revision: 0ff052588e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.060s	52.154s	48.444us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.870s	12.104s	61.474us	5	5	100.00
V1	csr_rw	edn_csr_rw	0.710s	6.066s	78.712us	3	3	100.00
V1	csr_bit_bash	edn_csr_bit_bash	3.610s	9.081s	248.969us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.150s	10.112s	32.630us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.260s	10.173s	106.508us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.710s	6.066s	78.712us	3	3	100.00
		edn_csr_aliasing	1.150s	10.112s	32.630us	5	5	100.00
V1		TOTAL				39	39	100.00
V2	firmware	edn_genbits	2.480s	1.019m	197.954us	10	10	100.00
V2	csrng_commands	edn_genbits	2.480s	1.019m	197.954us	10	10	100.00
V2	genbits	edn_genbits	2.480s	1.019m	197.954us	10	10	100.00
V2	interrupts	edn_intr	1.180s	1.502m	21.435us	8	8	100.00
V2	alerts	edn_alert	1.370s	1.370m	160.710us	29	29	100.00
V2	errs	edn_err	1.280s	1.303m	19.402us	8	8	100.00
V2	disable	edn_disable	1.080s	1.303m	15.585us	16	16	100.00
		edn_disable_auto_req_mode	1.500s	52.140s	47.829us	9	9	100.00
V2	stress_all	edn_stress_all	1.810s	1.035m	123.365us	1	1	100.00
V2	intr_test	edn_intr_test	0.830s	9.202s	15.438us	50	50	100.00
V2	alert_test	edn_alert_test	1.090s	52.144s	163.562us	3	3	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	2.660s	16.155s	599.816us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	2.660s	16.155s	599.816us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.870s	12.104s	61.474us	5	5	100.00
		edn_csr_rw	0.710s	6.066s	78.712us	3	3	100.00
		edn_csr_aliasing	1.150s	10.112s	32.630us	5	5	100.00
		edn_same_csr_outstanding	1.070s	13.140s	72.144us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.870s	12.104s	61.474us	5	5	100.00
		edn_csr_rw	0.710s	6.066s	78.712us	3	3	100.00
		edn_csr_aliasing	1.150s	10.112s	32.630us	5	5	100.00
		edn_same_csr_outstanding	1.070s	13.140s	72.144us	20	20	100.00
V2		TOTAL				174	174	100.00
V2S	tl_intg_err	edn_sec_cm	5.970s	59.183s	2.129ms	3	3	100.00
		edn_tl_intg_err	1.730s	11.104s	95.773us	3	3	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.110s	48.143s	19.801us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.370s	1.370m	160.710us	29	29	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	5.970s	59.183s	2.129ms	3	3	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	5.970s	59.183s	2.129ms	3	3	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	5.970s	59.183s	2.129ms	3	3	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	5.970s	59.183s	2.129ms	3	3	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.370s	1.370m	160.710us	29	29	100.00
		edn_sec_cm	5.970s	59.183s	2.129ms	3	3	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.370s	1.370m	160.710us	29	29	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	1.730s	11.104s	95.773us	3	3	100.00
V2S		TOTAL				16	16	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	40.860s	1.586m	3.009ms	7	7	100.00
V3		TOTAL				7	7	100.00
		TOTAL				236	236	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.48	98.91	94.14	97.12	84.41	96.51	97.61	92.66

Simulation Wall Clock Time

Target	Elapsed
build	00:07:13
run	30:46:43
cov_merge	30:47:37
cov_report	30:47:52
Total	30:47:52