EDN/EDN1 Simulation Results

Sunday August 02 2026 00:03:30 UTC

GitHub Revision: 0ff052588e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	0.620s	13.244s	25.280us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.650s	20.059s	32.452us	5	5	100.00
V1	csr_rw	edn_csr_rw	0.630s	17.060s	17.970us	3	3	100.00
V1	csr_bit_bash	edn_csr_bit_bash	3.020s	18.074s	1.048ms	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	0.890s	16.066s	39.160us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	0.980s	14.117s	51.218us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.630s	17.060s	17.970us	3	3	100.00
		edn_csr_aliasing	0.890s	16.066s	39.160us	5	5	100.00
V1		TOTAL				39	39	100.00
V2	firmware	edn_genbits	2.020s	22.090s	275.732us	10	10	100.00
V2	csrng_commands	edn_genbits	2.020s	22.090s	275.732us	10	10	100.00
V2	genbits	edn_genbits	2.020s	22.090s	275.732us	10	10	100.00
V2	interrupts	edn_intr	0.710s	22.085s	22.045us	8	8	100.00
V2	alerts	edn_alert	0.840s	22.091s	172.832us	26	26	100.00
V2	errs	edn_err	0.810s	22.092s	24.501us	8	8	100.00
V2	disable	edn_disable	0.640s	22.092s	14.328us	9	9	100.00
		edn_disable_auto_req_mode	0.800s	19.086s	41.730us	11	11	100.00
V2	stress_all	edn_stress_all	2.870s	17.225s	467.944us	4	4	100.00
V2	intr_test	edn_intr_test	0.630s	20.059s	16.487us	50	50	100.00
V2	alert_test	edn_alert_test	0.790s	14.143s	81.711us	3	3	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	2.600s	23.065s	1.191ms	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	2.600s	23.065s	1.191ms	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.650s	20.059s	32.452us	5	5	100.00
		edn_csr_rw	0.630s	17.060s	17.970us	3	3	100.00
		edn_csr_aliasing	0.890s	16.066s	39.160us	5	5	100.00
		edn_same_csr_outstanding	0.860s	14.116s	123.391us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.650s	20.059s	32.452us	5	5	100.00
		edn_csr_rw	0.630s	17.060s	17.970us	3	3	100.00
		edn_csr_aliasing	0.890s	16.066s	39.160us	5	5	100.00
		edn_same_csr_outstanding	0.860s	14.116s	123.391us	20	20	100.00
V2		TOTAL				169	169	100.00
V2S	tl_intg_err	edn_sec_cm	2.990s	24.098s	741.818us	4	4	100.00
		edn_tl_intg_err	1.860s	24.074s	251.600us	3	3	100.00
V2S	sec_cm_config_regwen	edn_regwen	0.650s	14.143s	28.069us	3	3	100.00
V2S	sec_cm_config_mubi	edn_alert	0.840s	22.091s	172.832us	26	26	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	2.990s	24.098s	741.818us	4	4	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	2.990s	24.098s	741.818us	4	4	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	2.990s	24.098s	741.818us	4	4	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	2.990s	24.098s	741.818us	4	4	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	0.840s	22.091s	172.832us	26	26	100.00
		edn_sec_cm	2.990s	24.098s	741.818us	4	4	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	0.840s	22.091s	172.832us	26	26	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	1.860s	24.074s	251.600us	3	3	100.00
V2S		TOTAL				10	10	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	51.940s	1.221m	5.446ms	6	6	100.00
V3		TOTAL				6	6	100.00
		TOTAL				224	224	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.30	98.48	94.92	96.15	86.36	94.59	97.14	92.44

Simulation Wall Clock Time

Target	Elapsed
build	00:07:13
run	30:46:43
cov_merge	30:47:37
cov_report	30:47:52
Total	30:47:52