ENTROPY_SRC/RNG16BITS Simulation Results

Sunday August 02 2026 00:03:30 UTC

GitHub Revision: 0ff052588e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	smoke	entropy_src_smoke	0.810s	5.157s	25.497us	1	1	100.00
V1	csr_hw_reset	entropy_src_csr_hw_reset	0.840s	9.116s	123.770us	6	6	100.00
V1	csr_rw	entropy_src_csr_rw	0.800s	7.084s	90.382us	3	3	100.00
V1	csr_bit_bash	entropy_src_csr_bit_bash	5.750s	14.196s	1.303ms	5	5	100.00
V1	csr_aliasing	entropy_src_csr_aliasing	2.580s	11.155s	226.156us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	entropy_src_csr_mem_rw_with_rand_reset	1.190s	9.124s	105.852us	3	3	100.00
V1	regwen_csr_and_corresponding_lockable_csr	entropy_src_csr_rw	0.800s	7.084s	90.382us	3	3	100.00
		entropy_src_csr_aliasing	2.580s	11.155s	226.156us	5	5	100.00
V1		TOTAL				23	23	100.00
V2	firmware	entropy_src_smoke	0.810s	5.157s	25.497us	1	1	100.00
		entropy_src_rng	5.978m	8.022m	16.036ms	59	59	100.00
		entropy_src_fw_ov	8.281m	9.580m	20.023ms	24	25	96.00
V2	firmware_mode	entropy_src_fw_ov	8.281m	9.580m	20.023ms	24	25	96.00
V2	rng_mode	entropy_src_rng	5.978m	8.022m	16.036ms	59	59	100.00
V2	rng_max_rate	entropy_src_rng_max_rate	12.800m	14.681m	18.069ms	60	60	100.00
V2	health_checks	entropy_src_rng	5.978m	8.022m	16.036ms	59	59	100.00
V2	conditioning	entropy_src_rng	5.978m	8.022m	16.036ms	59	59	100.00
V2	interrupts	entropy_src_rng	5.978m	8.022m	16.036ms	59	59	100.00
		entropy_src_intr	20.710s	3.159m	988.555us	12	12	100.00
V2	alerts	entropy_src_rng	5.978m	8.022m	16.036ms	59	59	100.00
		entropy_src_functional_alerts	4.130s	13.103s	172.469us	3	3	100.00
V2	stress_all	entropy_src_stress_all	7.261m	7.338m	20.132ms	6	6	100.00
V2	functional_errors	entropy_src_functional_errors	1.570s	3.042m	46.195us	192	192	100.00
V2	firmware_ov_read_contiguous_data	entropy_src_fw_ov_contiguous	4.060s	8.153s	1.052ms	1	1	100.00
V2	intr_test	entropy_src_intr_test	0.750s	9.145s	23.151us	50	50	100.00
V2	alert_test	entropy_src_alert_test	1.090s	12.075s	40.688us	3	3	100.00
V2	tl_d_oob_addr_access	entropy_src_tl_errors	2.540s	9.100s	659.232us	5	5	100.00
V2	tl_d_illegal_access	entropy_src_tl_errors	2.540s	9.100s	659.232us	5	5	100.00
V2	tl_d_outstanding_access	entropy_src_csr_hw_reset	0.840s	9.116s	123.770us	6	6	100.00
		entropy_src_csr_rw	0.800s	7.084s	90.382us	3	3	100.00
		entropy_src_csr_aliasing	2.580s	11.155s	226.156us	5	5	100.00
		entropy_src_same_csr_outstanding	1.340s	8.132s	96.810us	20	20	100.00
V2	tl_d_partial_access	entropy_src_csr_hw_reset	0.840s	9.116s	123.770us	6	6	100.00
		entropy_src_csr_rw	0.800s	7.084s	90.382us	3	3	100.00
		entropy_src_csr_aliasing	2.580s	11.155s	226.156us	5	5	100.00
		entropy_src_same_csr_outstanding	1.340s	8.132s	96.810us	20	20	100.00
V2		TOTAL				435	436	99.77
V2S	tl_intg_err	entropy_src_sec_cm	1.740s	11.068s	105.543us	3	3	100.00
		entropy_src_tl_intg_err	2.180s	11.152s	306.696us	16	16	100.00
V2S	sec_cm_config_regwen	entropy_src_rng	5.978m	8.022m	16.036ms	59	59	100.00
		entropy_src_cfg_regwen	1.060s	10.158s	22.337us	3	3	100.00
V2S	sec_cm_config_mubi	entropy_src_rng	5.978m	8.022m	16.036ms	59	59	100.00
V2S	sec_cm_config_redun	entropy_src_rng	5.978m	8.022m	16.036ms	59	59	100.00
V2S	sec_cm_intersig_mubi	entropy_src_rng	5.978m	8.022m	16.036ms	59	59	100.00
		entropy_src_fw_ov	8.281m	9.580m	20.023ms	24	25	96.00
V2S	sec_cm_main_sm_fsm_sparse	entropy_src_functional_errors	1.570s	3.042m	46.195us	192	192	100.00
		entropy_src_sec_cm	1.740s	11.068s	105.543us	3	3	100.00
V2S	sec_cm_ack_sm_fsm_sparse	entropy_src_functional_errors	1.570s	3.042m	46.195us	192	192	100.00
		entropy_src_sec_cm	1.740s	11.068s	105.543us	3	3	100.00
V2S	sec_cm_rng_bkgn_chk	entropy_src_rng	5.978m	8.022m	16.036ms	59	59	100.00
V2S	sec_cm_fifo_ctr_redun	entropy_src_functional_errors	1.570s	3.042m	46.195us	192	192	100.00
		entropy_src_sec_cm	1.740s	11.068s	105.543us	3	3	100.00
V2S	sec_cm_ctr_redun	entropy_src_functional_errors	1.570s	3.042m	46.195us	192	192	100.00
		entropy_src_sec_cm	1.740s	11.068s	105.543us	3	3	100.00
V2S	sec_cm_ctr_local_esc	entropy_src_functional_errors	1.570s	3.042m	46.195us	192	192	100.00
V2S	sec_cm_esfinal_rdata_bus_consistency	entropy_src_functional_alerts	4.130s	13.103s	172.469us	3	3	100.00
V2S	sec_cm_tile_link_bus_integrity	entropy_src_tl_intg_err	2.180s	11.152s	306.696us	16	16	100.00
V2S		TOTAL				22	22	100.00
V3	external_health_tests	entropy_src_rng_with_xht_rsps	6.972m	8.255m	19.017ms	10	10	100.00
V3	stress_all_with_rand_reset	entropy_src_stress_all_with_rand_reset				0	0	--
V3		TOTAL				10	10	100.00
		TOTAL				490	491	99.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	11	91.67
V2S	3	3	3	100.00
V3	2	1	1	50.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
86.52	97.56	90.02	77.37	62.07	95.55	89.43	93.67

Simulation Wall Clock Time

Target	Elapsed
build	00:07:13
run	30:46:43
cov_merge	30:47:37
cov_report	30:47:52
Total	30:47:52

Failure Buckets

• UVM_ERROR (cip_base_scoreboard.sv:357) scoreboard [scoreboard] alert recov_alert did not trigger max_delay:* has 1 failures:
  • Test entropy_src_fw_ov has 1 failures.

    • 24.entropy_src_fw_ov.3277934219572602623057050887074291529498864100850641547830405619017456134228
      Line 1315, in log /home/runner/_work/pavona/pavona/scratch/main/entropy_src_rng16bits-sim-vcs/24.entropy_src_fw_ov/latest/run.log

        UVM_ERROR @ 10272715524 ps: (cip_base_scoreboard.sv:357) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_alert did not trigger max_delay:4
        UVM_INFO @ 10272715524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---