ENTROPY_SRC/RNG4BITS Simulation Results

Sunday August 02 2026 00:03:30 UTC

GitHub Revision: 0ff052588e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	smoke	entropy_src_smoke	0.750s	11.074s	34.810us	1	1	100.00
V1	csr_hw_reset	entropy_src_csr_hw_reset	0.780s	11.099s	113.098us	4	4	100.00
V1	csr_rw	entropy_src_csr_rw	0.710s	12.077s	18.827us	3	3	100.00
V1	csr_bit_bash	entropy_src_csr_bit_bash	3.590s	13.129s	296.729us	5	5	100.00
V1	csr_aliasing	entropy_src_csr_aliasing	2.360s	12.092s	441.757us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	entropy_src_csr_mem_rw_with_rand_reset	1.080s	12.091s	422.834us	4	4	100.00
V1	regwen_csr_and_corresponding_lockable_csr	entropy_src_csr_rw	0.710s	12.077s	18.827us	3	3	100.00
		entropy_src_csr_aliasing	2.360s	12.092s	441.757us	5	5	100.00
V1		TOTAL				22	22	100.00
V2	firmware	entropy_src_smoke	0.750s	11.074s	34.810us	1	1	100.00
		entropy_src_rng	4.640m	6.279m	19.019ms	47	47	100.00
		entropy_src_fw_ov	4.729m	5.828m	16.053ms	20	24	83.33
V2	firmware_mode	entropy_src_fw_ov	4.729m	5.828m	16.053ms	20	24	83.33
V2	rng_mode	entropy_src_rng	4.640m	6.279m	19.019ms	47	47	100.00
V2	rng_max_rate	entropy_src_rng_max_rate	9.362m	10.262m	19.049ms	71	71	100.00
V2	health_checks	entropy_src_rng	4.640m	6.279m	19.019ms	47	47	100.00
V2	conditioning	entropy_src_rng	4.640m	6.279m	19.019ms	47	47	100.00
V2	interrupts	entropy_src_rng	4.640m	6.279m	19.019ms	47	47	100.00
		entropy_src_intr	13.120s	1.869m	1.955ms	10	10	100.00
V2	alerts	entropy_src_rng	4.640m	6.279m	19.019ms	47	47	100.00
		entropy_src_functional_alerts	2.560s	58.076s	708.630us	3	3	100.00
V2	stress_all	entropy_src_stress_all	3.219m	3.740m	18.276ms	5	5	100.00
V2	functional_errors	entropy_src_functional_errors	1.460s	2.438m	47.588us	67	67	100.00
V2	firmware_ov_read_contiguous_data	entropy_src_fw_ov_contiguous	1.810s	15.063s	218.361us	1	1	100.00
V2	intr_test	entropy_src_intr_test	0.700s	12.117s	19.773us	3	3	100.00
V2	alert_test	entropy_src_alert_test	0.690s	56.113s	27.908us	3	3	100.00
V2	tl_d_oob_addr_access	entropy_src_tl_errors	1.510s	12.111s	280.914us	5	5	100.00
V2	tl_d_illegal_access	entropy_src_tl_errors	1.510s	12.111s	280.914us	5	5	100.00
V2	tl_d_outstanding_access	entropy_src_csr_hw_reset	0.780s	11.099s	113.098us	4	4	100.00
		entropy_src_csr_rw	0.710s	12.077s	18.827us	3	3	100.00
		entropy_src_csr_aliasing	2.360s	12.092s	441.757us	5	5	100.00
		entropy_src_same_csr_outstanding	1.200s	14.085s	125.310us	20	20	100.00
V2	tl_d_partial_access	entropy_src_csr_hw_reset	0.780s	11.099s	113.098us	4	4	100.00
		entropy_src_csr_rw	0.710s	12.077s	18.827us	3	3	100.00
		entropy_src_csr_aliasing	2.360s	12.092s	441.757us	5	5	100.00
		entropy_src_same_csr_outstanding	1.200s	14.085s	125.310us	20	20	100.00
V2		TOTAL				255	259	98.46
V2S	tl_intg_err	entropy_src_sec_cm	1.330s	1.019m	488.968us	3	3	100.00
		entropy_src_tl_intg_err	2.200s	15.096s	810.309us	14	14	100.00
V2S	sec_cm_config_regwen	entropy_src_rng	4.640m	6.279m	19.019ms	47	47	100.00
		entropy_src_cfg_regwen	0.900s	1.135m	16.871us	3	3	100.00
V2S	sec_cm_config_mubi	entropy_src_rng	4.640m	6.279m	19.019ms	47	47	100.00
V2S	sec_cm_config_redun	entropy_src_rng	4.640m	6.279m	19.019ms	47	47	100.00
V2S	sec_cm_intersig_mubi	entropy_src_rng	4.640m	6.279m	19.019ms	47	47	100.00
		entropy_src_fw_ov	4.729m	5.828m	16.053ms	20	24	83.33
V2S	sec_cm_main_sm_fsm_sparse	entropy_src_functional_errors	1.460s	2.438m	47.588us	67	67	100.00
		entropy_src_sec_cm	1.330s	1.019m	488.968us	3	3	100.00
V2S	sec_cm_ack_sm_fsm_sparse	entropy_src_functional_errors	1.460s	2.438m	47.588us	67	67	100.00
		entropy_src_sec_cm	1.330s	1.019m	488.968us	3	3	100.00
V2S	sec_cm_rng_bkgn_chk	entropy_src_rng	4.640m	6.279m	19.019ms	47	47	100.00
V2S	sec_cm_fifo_ctr_redun	entropy_src_functional_errors	1.460s	2.438m	47.588us	67	67	100.00
		entropy_src_sec_cm	1.330s	1.019m	488.968us	3	3	100.00
V2S	sec_cm_ctr_redun	entropy_src_functional_errors	1.460s	2.438m	47.588us	67	67	100.00
		entropy_src_sec_cm	1.330s	1.019m	488.968us	3	3	100.00
V2S	sec_cm_ctr_local_esc	entropy_src_functional_errors	1.460s	2.438m	47.588us	67	67	100.00
V2S	sec_cm_esfinal_rdata_bus_consistency	entropy_src_functional_alerts	2.560s	58.076s	708.630us	3	3	100.00
V2S	sec_cm_tile_link_bus_integrity	entropy_src_tl_intg_err	2.200s	15.096s	810.309us	14	14	100.00
V2S		TOTAL				20	20	100.00
V3	external_health_tests	entropy_src_rng_with_xht_rsps	4.363m	5.801m	17.014ms	17	17	100.00
V3	stress_all_with_rand_reset	entropy_src_stress_all_with_rand_reset				0	0	--
V3		TOTAL				17	17	100.00
		TOTAL				314	318	98.74

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	11	91.67
V2S	3	3	3	100.00
V3	2	1	1	50.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
86.46	97.04	91.93	74.13	62.07	94.69	89.36	95.97

Simulation Wall Clock Time

Target	Elapsed
build	00:07:13
run	30:46:43
cov_merge	30:47:37
cov_report	30:47:52
Total	30:47:52

Failure Buckets

• UVM_ERROR (cip_base_scoreboard.sv:357) scoreboard [scoreboard] alert recov_alert did not trigger max_delay:* has 2 failures:

  • Test entropy_src_fw_ov has 2 failures.

    • 15.entropy_src_fw_ov.3738199498469126464474484286850146974247421302458748665903315974331703673494
      Line 1211, in log /home/runner/_work/pavona/pavona/scratch/main/entropy_src_rng4bits-sim-vcs/15.entropy_src_fw_ov/latest/run.log

        UVM_ERROR @ 6412443026 ps: (cip_base_scoreboard.sv:357) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_alert did not trigger max_delay:4
        UVM_INFO @ 6412443026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 19.entropy_src_fw_ov.112326292925002648828519155055668528701659760809299113489424801725304257144479
      Line 1517, in log /home/runner/_work/pavona/pavona/scratch/main/entropy_src_rng4bits-sim-vcs/19.entropy_src_fw_ov/latest/run.log

        UVM_ERROR @ 8055626628 ps: (cip_base_scoreboard.sv:357) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_alert did not trigger max_delay:4
        UVM_INFO @ 8055626628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:271) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_alert triggered unexpectedly has 2 failures:

  • Test entropy_src_fw_ov has 2 failures.

    • 17.entropy_src_fw_ov.105941802582609317520970173301721686888880699808133717907018757858369838775842
      Line 448, in log /home/runner/_work/pavona/pavona/scratch/main/entropy_src_rng4bits-sim-vcs/17.entropy_src_fw_ov/latest/run.log

        UVM_ERROR @ 4301483317 ps: (cip_base_scoreboard.sv:271) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_alert triggered unexpectedly
        UVM_INFO @ 4301483317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 22.entropy_src_fw_ov.39488194257557985653741056789976464250401953267443399410806344187263547980980
      Line 497, in log /home/runner/_work/pavona/pavona/scratch/main/entropy_src_rng4bits-sim-vcs/22.entropy_src_fw_ov/latest/run.log

        UVM_ERROR @ 1523431452 ps: (cip_base_scoreboard.sv:271) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_alert triggered unexpectedly
        UVM_INFO @ 1523431452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---