FLASH_CTRL/EGRET Simulation Results

Sunday August 02 2026 00:03:30 UTC

GitHub Revision: 0ff052588e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	1.470m	2.257m	30.040us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	15.850s	48.115s	19.819us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	13.780s	22.371s	59.845us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	10.510s	20.630s	79.416us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	31.340s	41.060s	2.208ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	32.680s	43.129s	2.565ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	10.310s	19.279s	51.513us	5	5	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	10.510s	20.630s	79.416us	20	20	100.00
		flash_ctrl_csr_aliasing	32.680s	43.129s	2.565ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	6.250s	17.256s	158.490us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	5.580s	17.265s	81.563us	5	5	100.00
V1		TOTAL				105	105	100.00
V2	sw_op	flash_ctrl_sw_op	20.380s	45.162s	28.874us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	1.012m	1.503m	836.737us	3	3	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	18.433m	19.515m	811.011ms	3	3	100.00
		flash_ctrl_hw_rma_reset	10.500m	11.416m	120.136ms	4	4	100.00
		flash_ctrl_lcmgr_intg	9.920s	49.191s	44.385us	4	4	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	28.371m	29.297m	272.827ms	7	7	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	4.612m	5.697m	57.139ms	3	3	100.00
V2	program_reset	flash_ctrl_prog_reset	2.530m	3.672m	5.890ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	26.168m	28.156m	382.456ms	3	3	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	1.079m	1.669m	1.529ms	3	3	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	21.690s	2.236m	186.205us	4	4	100.00
		flash_ctrl_rw_evict_all_en	20.120s	2.352m	28.277us	5	5	100.00
		flash_ctrl_re_evict	25.490s	2.586m	275.517us	5	5	100.00
V2	host_arb	flash_ctrl_phy_arb	2.613m	3.615m	3.098ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	2.613m	3.615m	3.098ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	3.354m	4.358m	10.782ms	3	3	100.00
V2	fetch_code	flash_ctrl_fetch_code	16.150s	2.036m	349.159us	4	4	100.00
V2	all_partitions	flash_ctrl_rand_ops	8.132m	8.610m	458.931us	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	8.793m	10.506m	6.593ms	3	3	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	5.871m	6.951m	312.962us	3	3	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	14.412m	15.494m	367.929us	3	3	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	8.590s	43.189s	39.707us	5	5	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	2.184m	3.854m	11.363ms	3	3	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	17.010s	1.702m	21.342us	12	12	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	12.870s	1.388m	13.572us	0	80	0.00
V2	stress_all	flash_ctrl_stress_all	8.928m	10.140m	1.378ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	2.054m	3.138m	6.354ms	3	3	100.00
		flash_ctrl_otp_reset	1.610m	2.888m	40.813us	8	8	100.00
V2	isolation_partition	flash_ctrl_hw_rma	18.433m	19.515m	811.011ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	2.956m	3.738m	3.703ms	5	6	83.33
		flash_ctrl_intr_wr	1.016m	2.803m	5.228ms	3	3	100.00
		flash_ctrl_intr_rd_slow_flash	4.178m	6.094m	54.540ms	4	4	100.00
		flash_ctrl_intr_wr_slow_flash	3.036m	4.991m	97.285ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	55.970s	2.654m	884.558us	3	3	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	47.490s	3.211m	1.803ms	3	3	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	16.290s	2.726m	71.594us	5	5	100.00
		flash_ctrl_ro_derr	1.672m	3.720m	3.034ms	3	3	100.00
		flash_ctrl_rw_derr	2.813m	5.290m	1.853ms	4	4	100.00
		flash_ctrl_derr_detect	1.558m	4.037m	969.118us	3	3	100.00
		flash_ctrl_integrity	6.585m	8.563m	16.883ms	5	5	100.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	17.050s	2.476m	46.769us	5	5	100.00
		flash_ctrl_ro_serr	1.914m	4.211m	3.072ms	4	4	100.00
		flash_ctrl_rw_serr	3.005m	5.046m	4.226ms	10	10	100.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.130m	3.360m	1.281ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.293m	3.543m	5.291ms	5	5	100.00
V2	scramble	flash_ctrl_wo	3.036m	4.295m	50.798ms	20	20	100.00
		flash_ctrl_write_word_sweep	9.880s	1.609m	94.604us	1	1	100.00
		flash_ctrl_read_word_sweep	9.020s	1.759m	91.261us	1	1	100.00
		flash_ctrl_ro	1.447m	3.372m	2.206ms	19	20	95.00
		flash_ctrl_rw	6.787m	8.570m	22.812ms	5	5	100.00
V2	filesystem_support	flash_ctrl_fs_sup	27.840s	1.136m	2.689ms	4	4	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	9.500m	10.063m	111.110ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	1.965m	2.310m	10.033ms	6	6	100.00
V2	alert_test	flash_ctrl_alert_test	9.320s	30.095s	90.519us	3	3	100.00
V2	intr_test	flash_ctrl_intr_test	5.610s	19.284s	19.424us	6	6	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	10.140s	19.522s	216.877us	8	8	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	10.140s	19.522s	216.877us	8	8	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	13.780s	22.371s	59.845us	5	5	100.00
		flash_ctrl_csr_rw	10.510s	20.630s	79.416us	20	20	100.00
		flash_ctrl_csr_aliasing	32.680s	43.129s	2.565ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	15.370s	23.838s	2.620ms	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	13.780s	22.371s	59.845us	5	5	100.00
		flash_ctrl_csr_rw	10.510s	20.630s	79.416us	20	20	100.00
		flash_ctrl_csr_aliasing	32.680s	43.129s	2.565ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	15.370s	23.838s	2.620ms	20	20	100.00
V2		TOTAL				344	426	80.75
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	35.500s	44.846s	141.426us	4	4	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	35.500s	44.846s	141.426us	4	4	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	35.500s	44.846s	141.426us	4	4	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	35.500s	44.846s	141.426us	4	4	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	44.710s	54.978s	444.891us	4	4	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.613m	2.973m	345.754us	0	5	0.00
		flash_ctrl_tl_intg_err	23.220s	31.531s	87.832us	0	20	0.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	23.220s	31.531s	87.832us	0	20	0.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	23.220s	31.531s	87.832us	0	20	0.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	20.020s	1.336m	64.130us	5	5	100.00
		flash_ctrl_wr_intg	10.310s	1.220m	47.665us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	1.470m	2.257m	30.040us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	1.610m	2.888m	40.813us	8	8	100.00
		flash_ctrl_disable	17.010s	1.702m	21.342us	12	12	100.00
		flash_ctrl_sec_info_access	51.330s	2.171m	15.336ms	12	12	100.00
		flash_ctrl_connect	12.870s	1.388m	13.572us	0	80	0.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	6.500s	44.131s	37.879us	3	3	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	10.510s	20.630s	79.416us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	35.500s	44.846s	141.426us	4	4	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	10.510s	20.630s	79.416us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	35.500s	44.846s	141.426us	4	4	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	10.510s	20.630s	79.416us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	35.500s	44.846s	141.426us	4	4	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	17.010s	1.702m	21.342us	12	12	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	20.020s	1.336m	64.130us	5	5	100.00
		flash_ctrl_access_after_disable	9.920s	1.404m	39.999us	6	6	100.00
V2S	sec_cm_mem_addr_infection	flash_ctrl_host_addr_infection	19.020s	44.123s	39.182us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	17.010s	1.702m	21.342us	12	12	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	16.150s	2.036m	349.159us	4	4	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	6.787m	8.570m	22.812ms	5	5	100.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	3.005m	5.046m	4.226ms	10	10	100.00
		flash_ctrl_rw_derr	2.813m	5.290m	1.853ms	4	4	100.00
		flash_ctrl_integrity	6.585m	8.563m	16.883ms	5	5	100.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	18.433m	19.515m	811.011ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.613m	2.973m	345.754us	0	5	0.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.613m	2.973m	345.754us	0	5	0.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.613m	2.973m	345.754us	0	5	0.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.613m	2.973m	345.754us	0	5	0.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	13.930s	1.403m	884.385us	10	10	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	9.050s	53.185s	355.090us	3	4	75.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	9.690s	53.139s	20.498us	4	4	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.613m	2.973m	345.754us	0	5	0.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.613m	2.973m	345.754us	0	5	0.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.613m	2.973m	345.754us	0	5	0.00
V2S		TOTAL				59	85	69.41
V3	asymmetric_read_path	flash_ctrl_rd_ooo	29.970s	55.143s	131.339us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset				0	0	--
V3		TOTAL				1	1	100.00
	Unmapped tests	flash_ctrl_basic_rw	6.075m	6.433m	527.673us	3	3	100.00
		TOTAL				512	620	82.58

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	9	9	9	100.00
V2	55	55	52	94.55
V2S	13	13	10	76.92
V3	2	1	1	50.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.33	95.49	94.43	95.39	87.18	96.69	94.41	96.75

Simulation Wall Clock Time

Target	Elapsed
build	00:07:13
run	30:46:43
cov_merge	30:47:37
cov_report	30:47:52
Total	30:47:52

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1268) [UVM/DPI/HDL_FORCE] set: unable to locate hdl path (tb.dut.cio_tck_i) has 80 failures:

  • Test flash_ctrl_connect has 80 failures.

    • 0.flash_ctrl_connect.70587115034364610400057860938725271405986687684249642886504805242943020106226
      Line 119, in log /home/runner/_work/pavona/pavona/scratch/main/flash_ctrl_top_egret-sim-vcs/0.flash_ctrl_connect/latest/run.log

        UVM_ERROR @ 4860.6 ns: (uvm_hdl_vcs.c:1268) [UVM/DPI/HDL_FORCE] set: unable to locate hdl path (tb.dut.cio_tck_i)
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_INFO @ 4860.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • 1.flash_ctrl_connect.54479311847860313885722095385647863421038858864266908170033214206047382801922
      Line 119, in log /home/runner/_work/pavona/pavona/scratch/main/flash_ctrl_top_egret-sim-vcs/1.flash_ctrl_connect/latest/run.log

        UVM_ERROR @ 18530.3 ns: (uvm_hdl_vcs.c:1268) [UVM/DPI/HDL_FORCE] set: unable to locate hdl path (tb.dut.cio_tck_i)
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_INFO @ 18530.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • ... and 78 more failures.

• UVM_ERROR (cip_base_vseq.sv:1023) virtual_sequencer [flash_ctrl_common_vseq] expect alert:fatal_std_err to fire has 16 failures:

  • Test flash_ctrl_sec_cm has 2 failures.

    • 0.flash_ctrl_sec_cm.88593279639179484913487772308586128488286289336274706312749627095680486157910
      Line 267, in log /home/runner/_work/pavona/pavona/scratch/main/flash_ctrl_top_egret-sim-vcs/0.flash_ctrl_sec_cm/latest/run.log

        UVM_ERROR @ 59991.3 ns: (cip_base_vseq.sv:1023) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.flash_ctrl_common_vseq] expect alert:fatal_std_err to fire
        UVM_INFO @ 59991.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.flash_ctrl_sec_cm.77791191048078639291005689475999023307810465616606087529043438436487391871313
      Line 176, in log /home/runner/_work/pavona/pavona/scratch/main/flash_ctrl_top_egret-sim-vcs/4.flash_ctrl_sec_cm/latest/run.log

        UVM_ERROR @ 12368.3 ns: (cip_base_vseq.sv:1023) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.flash_ctrl_common_vseq] expect alert:fatal_std_err to fire
        UVM_INFO @ 12368.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test flash_ctrl_tl_intg_err has 14 failures.

    • 0.flash_ctrl_tl_intg_err.107992270089266992965757338431374176690114747215456502379187938473678031883668
      Line 149, in log /home/runner/_work/pavona/pavona/scratch/main/flash_ctrl_top_egret-sim-vcs/0.flash_ctrl_tl_intg_err/latest/run.log

        UVM_ERROR @ 156052.5 ns: (cip_base_vseq.sv:1023) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.flash_ctrl_common_vseq] expect alert:fatal_std_err to fire
        UVM_INFO @ 156052.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.flash_ctrl_tl_intg_err.48406928749867788009912017579405576194837763611393131072016123293289998787690
      Line 155, in log /home/runner/_work/pavona/pavona/scratch/main/flash_ctrl_top_egret-sim-vcs/1.flash_ctrl_tl_intg_err/latest/run.log

        UVM_ERROR @ 67231.0 ns: (cip_base_vseq.sv:1023) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.flash_ctrl_common_vseq] expect alert:fatal_std_err to fire
        UVM_INFO @ 67231.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 12 more failures.

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.std_fault_status.reg_intg_err reset value: * has 9 failures:

  • Test flash_ctrl_sec_cm has 3 failures.

    • 1.flash_ctrl_sec_cm.106033414340560839614855976921285398227216756442675638476877358082095422298565
      Line 788, in log /home/runner/_work/pavona/pavona/scratch/main/flash_ctrl_top_egret-sim-vcs/1.flash_ctrl_sec_cm/latest/run.log

        UVM_ERROR @ 345754.4 ns: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.std_fault_status.reg_intg_err reset value: 0x0
        UVM_INFO @ 345754.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.flash_ctrl_sec_cm.109928731548705412646780261154885635091765622049811370158926479080361382103490
      Line 136, in log /home/runner/_work/pavona/pavona/scratch/main/flash_ctrl_top_egret-sim-vcs/2.flash_ctrl_sec_cm/latest/run.log

        UVM_ERROR @ 7509.0 ns: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.std_fault_status.reg_intg_err reset value: 0x0
        UVM_INFO @ 7509.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

  • Test flash_ctrl_tl_intg_err has 6 failures.

    • 3.flash_ctrl_tl_intg_err.88205080734540076327043617435103131615515280015037571428542555398057214525052
      Line 153, in log /home/runner/_work/pavona/pavona/scratch/main/flash_ctrl_top_egret-sim-vcs/3.flash_ctrl_tl_intg_err/latest/run.log

        UVM_ERROR @ 87831.7 ns: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.std_fault_status.reg_intg_err reset value: 0x0
        UVM_INFO @ 87831.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.flash_ctrl_tl_intg_err.93773826620801698114616887390619528284764098018751260164527754741208061606031
      Line 149, in log /home/runner/_work/pavona/pavona/scratch/main/flash_ctrl_top_egret-sim-vcs/4.flash_ctrl_tl_intg_err/latest/run.log

        UVM_ERROR @ 221895.0 ns: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.std_fault_status.reg_intg_err reset value: 0x0
        UVM_INFO @ 221895.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 4 more failures.

• Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))' has 1 failures:

  • Test flash_ctrl_phy_host_grant_err has 1 failures.

    • 2.flash_ctrl_phy_host_grant_err.38735650772001246616676603749664201958434694902707230337583776552912211581593
      Line 136, in log /home/runner/_work/pavona/pavona/scratch/main/flash_ctrl_top_egret-sim-vcs/2.flash_ctrl_phy_host_grant_err/latest/run.log

            Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))'
        UVM_ERROR @ 29187.8 ns: (alert_esc_if.sv:202) [ASSERT FAILED] AlertKnown_A
        UVM_INFO @ 29187.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:271) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 1 failures:

  • Test flash_ctrl_ro has 1 failures.

    • 3.flash_ctrl_ro.57469279615240740539383218039865311428873643550306371729090562814880468063910
      Line 119, in log /home/runner/_work/pavona/pavona/scratch/main/flash_ctrl_top_egret-sim-vcs/3.flash_ctrl_ro/latest/run.log

        UVM_ERROR @ 753276.1 ns: (cip_base_scoreboard.sv:271) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
        UVM_INFO @ 753276.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] *: obs:exp *c1e3dd_d531f7dc:ffffffff_d531f7dc mismatch!! has 1 failures:

  • Test flash_ctrl_intr_rd has 1 failures.

    • 5.flash_ctrl_intr_rd.72110560301569600651675455112485720276623178327753628906359844331037616841977
      Line 119, in log /home/runner/_work/pavona/pavona/scratch/main/flash_ctrl_top_egret-sim-vcs/5.flash_ctrl_intr_rd/latest/run.log

        UVM_ERROR @ 1526425.7 ns: (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1]    5: obs:exp    07c1e3dd_d531f7dc:ffffffff_d531f7dc  mismatch!!
        UVM_INFO @ 1526425.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---