0ff052588e| Stage | Name | Tests | Max Job Runtime | Max Wall Clock | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|---|
| V1 | smoke | gpio_smoke | 1.160s | 10.334s | 1.123ms | 1 | 1 | 100.00 |
| gpio_smoke_no_pullup_pulldown | 0.980s | 10.344s | 77.364us | 1 | 1 | 100.00 | ||
| gpio_smoke_en_cdc_prim | 1.280s | 40.227s | 54.851us | 1 | 1 | 100.00 | ||
| gpio_smoke_no_pullup_pulldown_en_cdc_prim | 1.510s | 40.252s | 401.792us | 1 | 1 | 100.00 | ||
| V1 | csr_hw_reset | gpio_csr_hw_reset | 0.940s | 11.188s | 21.578us | 5 | 5 | 100.00 |
| V1 | csr_rw | gpio_csr_rw | 0.890s | 10.127s | 14.726us | 2 | 3 | 66.67 |
| V1 | csr_bit_bash | gpio_csr_bit_bash | 5.530s | 12.202s | 799.033us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | gpio_csr_aliasing | 2.050s | 11.189s | 55.076us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | gpio_csr_mem_rw_with_rand_reset | 1.230s | 10.128s | 46.101us | 3 | 3 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | gpio_csr_rw | 0.890s | 10.127s | 14.726us | 2 | 3 | 66.67 |
| gpio_csr_aliasing | 2.050s | 11.189s | 55.076us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 24 | 25 | 96.00 | ||||
| V2 | direct_and_masked_out | gpio_random_dout_din | 0.930s | 10.337s | 114.609us | 1 | 1 | 100.00 |
| gpio_random_dout_din_no_pullup_pulldown | 0.790s | 9.320s | 26.319us | 1 | 1 | 100.00 | ||
| V2 | out_in_regs_read_write | gpio_dout_din_regs_random_rw | 0.730s | 9.316s | 22.898us | 1 | 1 | 100.00 |
| V2 | gpio_interrupt_programming | gpio_intr_rand_pgm | 0.870s | 8.293s | 47.158us | 1 | 1 | 100.00 |
| V2 | random_interrupt_trigger | gpio_rand_intr_trigger | 0.830s | 6.252s | 27.124us | 1 | 1 | 100.00 |
| V2 | interrupt_and_noise_filter | gpio_intr_with_filter_rand_intr_event | 3.530s | 13.120s | 338.445us | 3 | 3 | 100.00 |
| V2 | noise_filter_stress | gpio_filter_stress | 10.690s | 19.289s | 734.293us | 1 | 1 | 100.00 |
| V2 | regs_long_reads_and_writes | gpio_random_long_reg_writes_reg_reads | 3.250s | 12.177s | 393.252us | 1 | 1 | 100.00 |
| V2 | full_random | gpio_full_random | 0.830s | 9.151s | 113.507us | 1 | 1 | 100.00 |
| V2 | stress_all | gpio_stress_all | 1.831m | 1.939m | 14.273ms | 3 | 3 | 100.00 |
| V2 | alert_test | gpio_alert_test | 0.710s | 9.083s | 48.219us | 3 | 3 | 100.00 |
| V2 | intr_test | gpio_intr_test | 0.800s | 10.123s | 51.030us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | gpio_tl_errors | 2.330s | 11.137s | 1.736ms | 3 | 3 | 100.00 |
| V2 | tl_d_illegal_access | gpio_tl_errors | 2.330s | 11.137s | 1.736ms | 3 | 3 | 100.00 |
| V2 | tl_d_outstanding_access | gpio_csr_rw | 0.890s | 10.127s | 14.726us | 2 | 3 | 66.67 |
| gpio_same_csr_outstanding | 1.240s | 10.193s | 213.215us | 16 | 20 | 80.00 | ||
| gpio_csr_aliasing | 2.050s | 11.189s | 55.076us | 5 | 5 | 100.00 | ||
| gpio_csr_hw_reset | 0.940s | 11.188s | 21.578us | 5 | 5 | 100.00 | ||
| V2 | tl_d_partial_access | gpio_csr_rw | 0.890s | 10.127s | 14.726us | 2 | 3 | 66.67 |
| gpio_same_csr_outstanding | 1.240s | 10.193s | 213.215us | 16 | 20 | 80.00 | ||
| gpio_csr_aliasing | 2.050s | 11.189s | 55.076us | 5 | 5 | 100.00 | ||
| gpio_csr_hw_reset | 0.940s | 11.188s | 21.578us | 5 | 5 | 100.00 | ||
| V2 | TOTAL | 86 | 90 | 95.56 | ||||
| V2S | tl_intg_err | gpio_tl_intg_err | 2.190s | 11.193s | 799.056us | 12 | 13 | 92.31 |
| gpio_sec_cm | 1.120s | 10.097s | 661.365us | 3 | 3 | 100.00 | ||
| V2S | sec_cm_bus_integrity | gpio_tl_intg_err | 2.190s | 11.193s | 799.056us | 12 | 13 | 92.31 |
| V2S | TOTAL | 15 | 16 | 93.75 | ||||
| V3 | straps_data | gpio_rand_straps | 0.540s | 5.067s | 70.775us | 1 | 1 | 100.00 |
| V3 | stress_all_with_rand_reset | gpio_stress_all_with_rand_reset | 1.270s | 8.126s | 8.789us | 0 | 1 | 0.00 |
| V3 | TOTAL | 1 | 2 | 50.00 | ||||
| Unmapped tests | gpio_inp_prd_cnt | 0.800s | 10.142s | 145.947us | 13 | 13 | 100.00 | |
| TOTAL | 139 | 146 | 95.21 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 1 | 100.00 |
| V1 | 9 | 9 | 8 | 88.89 |
| V2 | 14 | 14 | 13 | 92.86 |
| V2S | 2 | 2 | 1 | 50.00 |
| V3 | 2 | 2 | 1 | 50.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 92.38 | 99.89 | 95.68 | 80.88 | 75.00 | 98.38 | 96.84 | 100.00 |
| Target | Elapsed |
|---|---|
| build | 00:07:13 |
| run | 30:46:43 |
| cov_merge | 30:47:37 |
| cov_report | 30:47:52 |
| Total | 30:47:52 |
UVM_ERROR (cip_base_vseq.sv:649) [gpio_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 4 failures:
0.gpio_same_csr_outstanding.102871655133182412725947246064706978126751733469319541231589669545382710120904
Line 86, in log /home/runner/_work/pavona/pavona/scratch/main/gpio_top_dragonfly-sim-vcs/0.gpio_same_csr_outstanding/latest/run.log
UVM_ERROR @ 213214795 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed masked_data == exp_data (1086724 [0x109504] vs 1086725 [0x109505]) addr 0x3fe1dd58 read out mismatch
UVM_INFO @ 213214795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.gpio_same_csr_outstanding.83127960243558526615642254453887754797993402195262193393336209739641944200970
Line 84, in log /home/runner/_work/pavona/pavona/scratch/main/gpio_top_dragonfly-sim-vcs/5.gpio_same_csr_outstanding/latest/run.log
UVM_ERROR @ 36403021 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed masked_data == exp_data (8895748 [0x87bd04] vs 8895749 [0x87bd05]) addr 0xd35b3658 read out mismatch
UVM_INFO @ 36403021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (cip_base_vseq.sv:1171) [gpio_common_vseq] Check failed (vseq_done) has 1 failures:
0.gpio_stress_all_with_rand_reset.106794505182721221195048210215917789537237519022450886753187482429893249841260
Line 87, in log /home/runner/_work/pavona/pavona/scratch/main/gpio_top_dragonfly-sim-vcs/0.gpio_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 8788788 ps: (cip_base_vseq.sv:1171) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (vseq_done)
UVM_INFO @ 8788788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: gpio_reg_block.inp_prd_cnt_val_* reset value: * has 1 failures:
2.gpio_csr_rw.53181660844963028376963350698051421380490651763545978075392400555753332649700
Line 80, in log /home/runner/_work/pavona/pavona/scratch/main/gpio_top_dragonfly-sim-vcs/2.gpio_csr_rw/latest/run.log
UVM_ERROR @ 34899002 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (3 [0x3] vs 0 [0x0]) Regname: gpio_reg_block.inp_prd_cnt_val_0 reset value: 0x0
UVM_INFO @ 34899002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: gpio_reg_block.inp_prd_cnt_ctrl_* reset value: * has 1 failures:
11.gpio_tl_intg_err.85745167399318327838460793727609710470623124912273116899460635530899029322177
Line 92, in log /home/runner/_work/pavona/pavona/scratch/main/gpio_top_dragonfly-sim-vcs/11.gpio_tl_intg_err/latest/run.log
UVM_ERROR @ 17004824 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (3921924 [0x3bd804] vs 3921925 [0x3bd805]) Regname: gpio_reg_block.inp_prd_cnt_ctrl_2 reset value: 0x4
UVM_INFO @ 17004824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---