GPIO/DRAGONFLY Simulation Results

Sunday August 02 2026 00:03:30 UTC

GitHub Revision: 0ff052588e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Max Wall Clock Simulated Time Passing Total Pass Rate
V1 smoke gpio_smoke 1.160s 10.334s 1.123ms 1 1 100.00
gpio_smoke_no_pullup_pulldown 0.980s 10.344s 77.364us 1 1 100.00
gpio_smoke_en_cdc_prim 1.280s 40.227s 54.851us 1 1 100.00
gpio_smoke_no_pullup_pulldown_en_cdc_prim 1.510s 40.252s 401.792us 1 1 100.00
V1 csr_hw_reset gpio_csr_hw_reset 0.940s 11.188s 21.578us 5 5 100.00
V1 csr_rw gpio_csr_rw 0.890s 10.127s 14.726us 2 3 66.67
V1 csr_bit_bash gpio_csr_bit_bash 5.530s 12.202s 799.033us 5 5 100.00
V1 csr_aliasing gpio_csr_aliasing 2.050s 11.189s 55.076us 5 5 100.00
V1 csr_mem_rw_with_rand_reset gpio_csr_mem_rw_with_rand_reset 1.230s 10.128s 46.101us 3 3 100.00
V1 regwen_csr_and_corresponding_lockable_csr gpio_csr_rw 0.890s 10.127s 14.726us 2 3 66.67
gpio_csr_aliasing 2.050s 11.189s 55.076us 5 5 100.00
V1 TOTAL 24 25 96.00
V2 direct_and_masked_out gpio_random_dout_din 0.930s 10.337s 114.609us 1 1 100.00
gpio_random_dout_din_no_pullup_pulldown 0.790s 9.320s 26.319us 1 1 100.00
V2 out_in_regs_read_write gpio_dout_din_regs_random_rw 0.730s 9.316s 22.898us 1 1 100.00
V2 gpio_interrupt_programming gpio_intr_rand_pgm 0.870s 8.293s 47.158us 1 1 100.00
V2 random_interrupt_trigger gpio_rand_intr_trigger 0.830s 6.252s 27.124us 1 1 100.00
V2 interrupt_and_noise_filter gpio_intr_with_filter_rand_intr_event 3.530s 13.120s 338.445us 3 3 100.00
V2 noise_filter_stress gpio_filter_stress 10.690s 19.289s 734.293us 1 1 100.00
V2 regs_long_reads_and_writes gpio_random_long_reg_writes_reg_reads 3.250s 12.177s 393.252us 1 1 100.00
V2 full_random gpio_full_random 0.830s 9.151s 113.507us 1 1 100.00
V2 stress_all gpio_stress_all 1.831m 1.939m 14.273ms 3 3 100.00
V2 alert_test gpio_alert_test 0.710s 9.083s 48.219us 3 3 100.00
V2 intr_test gpio_intr_test 0.800s 10.123s 51.030us 50 50 100.00
V2 tl_d_oob_addr_access gpio_tl_errors 2.330s 11.137s 1.736ms 3 3 100.00
V2 tl_d_illegal_access gpio_tl_errors 2.330s 11.137s 1.736ms 3 3 100.00
V2 tl_d_outstanding_access gpio_csr_rw 0.890s 10.127s 14.726us 2 3 66.67
gpio_same_csr_outstanding 1.240s 10.193s 213.215us 16 20 80.00
gpio_csr_aliasing 2.050s 11.189s 55.076us 5 5 100.00
gpio_csr_hw_reset 0.940s 11.188s 21.578us 5 5 100.00
V2 tl_d_partial_access gpio_csr_rw 0.890s 10.127s 14.726us 2 3 66.67
gpio_same_csr_outstanding 1.240s 10.193s 213.215us 16 20 80.00
gpio_csr_aliasing 2.050s 11.189s 55.076us 5 5 100.00
gpio_csr_hw_reset 0.940s 11.188s 21.578us 5 5 100.00
V2 TOTAL 86 90 95.56
V2S tl_intg_err gpio_tl_intg_err 2.190s 11.193s 799.056us 12 13 92.31
gpio_sec_cm 1.120s 10.097s 661.365us 3 3 100.00
V2S sec_cm_bus_integrity gpio_tl_intg_err 2.190s 11.193s 799.056us 12 13 92.31
V2S TOTAL 15 16 93.75
V3 straps_data gpio_rand_straps 0.540s 5.067s 70.775us 1 1 100.00
V3 stress_all_with_rand_reset gpio_stress_all_with_rand_reset 1.270s 8.126s 8.789us 0 1 0.00
V3 TOTAL 1 2 50.00
Unmapped tests gpio_inp_prd_cnt 0.800s 10.142s 145.947us 13 13 100.00
TOTAL 139 146 95.21

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 1 100.00
V1 9 9 8 88.89
V2 14 14 13 92.86
V2S 2 2 1 50.00
V3 2 2 1 50.00

Coverage Results

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
92.38 99.89 95.68 80.88 75.00 98.38 96.84 100.00

Simulation Wall Clock Time

Target Elapsed
build 00:07:13
run 30:46:43
cov_merge 30:47:37
cov_report 30:47:52
Total 30:47:52

Failure Buckets