GPIO/EGRET Simulation Results

Sunday August 02 2026 00:03:30 UTC

GitHub Revision: 0ff052588e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	0.690s	5.058s	41.529us	1	1	100.00
		gpio_smoke_no_pullup_pulldown	0.740s	5.057s	190.545us	1	1	100.00
		gpio_smoke_en_cdc_prim	0.660s	5.101s	108.701us	1	1	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	0.800s	5.102s	46.663us	1	1	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.550s	6.140s	47.854us	3	3	100.00
V1	csr_rw	gpio_csr_rw	0.510s	7.148s	38.961us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	1.700s	8.131s	1.768ms	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.620s	7.147s	138.435us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	0.660s	7.215s	88.933us	3	3	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.510s	7.148s	38.961us	20	20	100.00
		gpio_csr_aliasing	0.620s	7.147s	138.435us	5	5	100.00
V1		TOTAL				40	40	100.00
V2	direct_and_masked_out	gpio_random_dout_din	0.640s	5.056s	197.031us	1	1	100.00
		gpio_random_dout_din_no_pullup_pulldown	0.610s	6.062s	71.947us	1	1	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	0.550s	6.063s	91.758us	1	1	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	0.650s	5.054s	33.096us	1	1	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	1.250s	5.054s	293.480us	1	1	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	1.700s	6.070s	88.026us	3	3	100.00
V2	noise_filter_stress	gpio_filter_stress	6.750s	11.128s	1.184ms	1	1	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	2.970s	8.084s	1.443ms	1	1	100.00
V2	full_random	gpio_full_random	0.510s	5.055s	356.565us	1	1	100.00
V2	stress_all	gpio_stress_all	41.530s	46.161s	26.186ms	3	3	100.00
V2	alert_test	gpio_alert_test	0.470s	9.099s	12.626us	3	3	100.00
V2	intr_test	gpio_intr_test	0.520s	6.102s	16.334us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	1.350s	5.195s	119.295us	3	3	100.00
V2	tl_d_illegal_access	gpio_tl_errors	1.350s	5.195s	119.295us	3	3	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.510s	7.148s	38.961us	20	20	100.00
		gpio_same_csr_outstanding	0.660s	6.138s	130.385us	3	3	100.00
		gpio_csr_aliasing	0.620s	7.147s	138.435us	5	5	100.00
		gpio_csr_hw_reset	0.550s	6.140s	47.854us	3	3	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.510s	7.148s	38.961us	20	20	100.00
		gpio_same_csr_outstanding	0.660s	6.138s	130.385us	3	3	100.00
		gpio_csr_aliasing	0.620s	7.147s	138.435us	5	5	100.00
		gpio_csr_hw_reset	0.550s	6.140s	47.854us	3	3	100.00
V2		TOTAL				73	73	100.00
V2S	tl_intg_err	gpio_tl_intg_err	0.960s	6.102s	2.224ms	8	8	100.00
		gpio_sec_cm	0.590s	7.081s	40.897us	3	3	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	0.960s	6.102s	2.224ms	8	8	100.00
V2S		TOTAL				11	11	100.00
V3	straps_data	gpio_rand_straps	0.450s	5.053s	16.111us	1	1	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	1.980s	6.062s	433.960us	0	1	0.00
V3		TOTAL				1	2	50.00
		TOTAL				125	126	99.21

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.08	99.76	99.57	80.52	--	99.80	96.84	100.00

Simulation Wall Clock Time

Target	Elapsed
build	00:07:13
run	30:46:43
cov_merge	30:47:37
cov_report	30:47:52
Total	30:47:52

Failure Buckets

• UVM_FATAL sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -* has 1 failures:
  • Test gpio_stress_all_with_rand_reset has 1 failures.

    • 0.gpio_stress_all_with_rand_reset.95828235704870858020589155035881294549908938044029238720166017020170095817280
      Line 168, in log /home/runner/_work/pavona/pavona/scratch/main/gpio_top_egret-sim-vcs/0.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 433960266 ps: uvm_test_top.env.m_tl_agent_gpio_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
        UVM_INFO @ 433960266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---