HMAC Simulation Results

Sunday August 02 2026 00:03:30 UTC

GitHub Revision: 0ff052588e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	6.950s	36.149s	2.918ms	1	1	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	0.730s	47.365s	37.537us	5	5	100.00
V1	csr_rw	hmac_csr_rw	0.620s	47.349s	29.026us	3	3	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	8.800s	52.347s	1.653ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	4.760s	43.313s	2.122ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	9.328m	9.750m	600.641ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.620s	47.349s	29.026us	3	3	100.00
		hmac_csr_aliasing	4.760s	43.313s	2.122ms	5	5	100.00
V1		TOTAL				39	39	100.00
V2	long_msg	hmac_long_msg	20.540s	50.181s	731.477us	1	1	100.00
V2	back_pressure	hmac_back_pressure	45.260s	1.734m	1.209ms	4	4	100.00
V2	test_vectors	hmac_test_sha256_vectors	3.000m	6.372m	9.312ms	11	11	100.00
		hmac_test_sha384_vectors	5.886m	8.110m	49.821ms	23	23	100.00
		hmac_test_sha512_vectors	5.903m	9.461m	12.786ms	24	24	100.00
		hmac_test_hmac256_vectors	11.540s	3.716m	1.289ms	17	17	100.00
		hmac_test_hmac384_vectors	10.460s	3.498m	1.524ms	29	29	100.00
		hmac_test_hmac512_vectors	16.080s	3.520m	433.559us	32	32	100.00
V2	burst_wr	hmac_burst_wr	17.670s	1.600m	640.858us	4	4	100.00
V2	datapath_stress	hmac_datapath_stress	7.484m	7.964m	18.828ms	1	1	100.00
V2	error	hmac_error	47.410s	1.634m	2.436ms	3	3	100.00
V2	wipe_secret	hmac_wipe_secret	40.050s	1.227m	2.541ms	1	1	100.00
V2	save_and_restore	hmac_smoke	6.950s	36.149s	2.918ms	1	1	100.00
		hmac_long_msg	20.540s	50.181s	731.477us	1	1	100.00
		hmac_back_pressure	45.260s	1.734m	1.209ms	4	4	100.00
		hmac_datapath_stress	7.484m	7.964m	18.828ms	1	1	100.00
		hmac_burst_wr	17.670s	1.600m	640.858us	4	4	100.00
		hmac_stress_all	20.170m	21.394m	43.106ms	8	8	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	6.950s	36.149s	2.918ms	1	1	100.00
		hmac_long_msg	20.540s	50.181s	731.477us	1	1	100.00
		hmac_back_pressure	45.260s	1.734m	1.209ms	4	4	100.00
		hmac_datapath_stress	7.484m	7.964m	18.828ms	1	1	100.00
		hmac_wipe_secret	40.050s	1.227m	2.541ms	1	1	100.00
		hmac_test_sha256_vectors	3.000m	6.372m	9.312ms	11	11	100.00
		hmac_test_sha384_vectors	5.886m	8.110m	49.821ms	23	23	100.00
		hmac_test_sha512_vectors	5.903m	9.461m	12.786ms	24	24	100.00
		hmac_test_hmac256_vectors	11.540s	3.716m	1.289ms	17	17	100.00
		hmac_test_hmac384_vectors	10.460s	3.498m	1.524ms	29	29	100.00
		hmac_test_hmac512_vectors	16.080s	3.520m	433.559us	32	32	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	6.950s	36.149s	2.918ms	1	1	100.00
		hmac_long_msg	20.540s	50.181s	731.477us	1	1	100.00
		hmac_back_pressure	45.260s	1.734m	1.209ms	4	4	100.00
		hmac_datapath_stress	7.484m	7.964m	18.828ms	1	1	100.00
		hmac_burst_wr	17.670s	1.600m	640.858us	4	4	100.00
		hmac_error	47.410s	1.634m	2.436ms	3	3	100.00
		hmac_wipe_secret	40.050s	1.227m	2.541ms	1	1	100.00
		hmac_test_sha256_vectors	3.000m	6.372m	9.312ms	11	11	100.00
		hmac_test_sha384_vectors	5.886m	8.110m	49.821ms	23	23	100.00
		hmac_test_sha512_vectors	5.903m	9.461m	12.786ms	24	24	100.00
		hmac_test_hmac256_vectors	11.540s	3.716m	1.289ms	17	17	100.00
		hmac_test_hmac384_vectors	10.460s	3.498m	1.524ms	29	29	100.00
		hmac_test_hmac512_vectors	16.080s	3.520m	433.559us	32	32	100.00
		hmac_stress_all	20.170m	21.394m	43.106ms	8	8	100.00
V2	stress_all	hmac_stress_all	20.170m	21.394m	43.106ms	8	8	100.00
V2	alert_test	hmac_alert_test	0.640s	1.291m	37.316us	3	3	100.00
V2	intr_test	hmac_intr_test	0.640s	47.365s	53.123us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	2.120s	52.766s	345.417us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	2.120s	52.766s	345.417us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	0.730s	47.365s	37.537us	5	5	100.00
		hmac_csr_rw	0.620s	47.349s	29.026us	3	3	100.00
		hmac_csr_aliasing	4.760s	43.313s	2.122ms	5	5	100.00
		hmac_same_csr_outstanding	1.430s	40.292s	114.590us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	0.730s	47.365s	37.537us	5	5	100.00
		hmac_csr_rw	0.620s	47.349s	29.026us	3	3	100.00
		hmac_csr_aliasing	4.760s	43.313s	2.122ms	5	5	100.00
		hmac_same_csr_outstanding	1.430s	40.292s	114.590us	20	20	100.00
V2		TOTAL				251	251	100.00
V2S	tl_intg_err	hmac_sec_cm	1.070s	1.308m	186.448us	3	3	100.00
		hmac_tl_intg_err	2.700s	50.410s	536.319us	5	5	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	2.700s	50.410s	536.319us	5	5	100.00
V2S		TOTAL				8	8	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	6.950s	36.149s	2.918ms	1	1	100.00
V3	stress_reset	hmac_stress_reset	1.540s	1.030m	1.075ms	3	3	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	14.376m	17.834m	434.490ms	9	9	100.00
V3		TOTAL				12	12	100.00
	Unmapped tests	hmac_directed	1.380s	1.291m	92.038us	3	3	100.00
		TOTAL				313	313	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	6	6	6	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	2	100.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.31	99.59	96.45	100.00	97.14	97.59	97.36	100.00

Simulation Wall Clock Time

Target	Elapsed
build	00:07:13
run	30:46:43
cov_merge	30:47:37
cov_report	30:47:52
Total	30:47:52