I2C Simulation Results

Sunday August 02 2026 00:03:30 UTC

GitHub Revision: `0ff052588e`

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	15.030s	24.291s	7.339ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	14.000s	23.137s	673.224us	5	5	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.610s	9.155s	27.196us	5	5	100.00
V1	csr_rw	i2c_csr_rw	6.370s	14.133s	10.721ms	5	5	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	2.690s	9.128s	364.111us	5	5	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.190s	7.058s	92.811us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	0.810s	10.083s	26.819us	3	3	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	6.370s	14.133s	10.721ms	5	5	100.00
		i2c_csr_aliasing	1.190s	7.058s	92.811us	5	5	100.00
V1		TOTAL				29	29	100.00
V2	host_error_intr	i2c_host_error_intr	2.860s	12.061s	515.276us	3	5	60.00
V2	host_stress_all	i2c_host_stress_all	21.596m	21.752m	16.650ms	6	7	85.71
V2	host_maxperf	i2c_host_perf	16.015m	16.238m	27.794ms	5	5	100.00
V2	host_override	i2c_host_override	0.840s	16.125s	15.997us	4	4	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	3.542m	3.705m	4.885ms	3	3	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	47.800s	53.491s	2.510ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.220s	14.127s	380.163us	5	5	100.00
		i2c_host_fifo_fmt_empty	3.000s	9.187s	255.130us	1	1	100.00
		i2c_host_fifo_reset_rx	7.110s	16.121s	188.344us	3	3	100.00
V2	host_fifo_full	i2c_host_fifo_full	1.654m	1.730m	24.180ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	17.140s	25.213s	2.585ms	1	1	100.00
V2	host_rx_oversample	host_rx_oversample				0	0	--
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	2.530s	28.078s	469.853us	3	5	60.00
V2	target_glitch	i2c_target_glitch	2.930s	12.151s	548.399us	0	2	0.00
V2	target_stress_all	i2c_target_stress_all	54.030s	1.124m	56.886ms	3	3	100.00
V2	target_maxperf	i2c_target_perf	4.410s	17.066s	3.245ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	36.750s	45.321s	1.304ms	3	3	100.00
		i2c_target_intr_smoke	4.480s	15.109s	9.043ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.450s	14.138s	786.358us	5	5	100.00
		i2c_target_fifo_reset_tx	1.590s	7.027s	1.836ms	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	32.200s	39.289s	54.700ms	4	4	100.00
		i2c_target_stress_rd	36.750s	45.321s	1.304ms	3	3	100.00
		i2c_target_intr_stress_wr	2.322m	2.397m	16.734ms	4	4	100.00
V2	target_timeout	i2c_target_timeout	3.250s	7.071s	968.662us	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	15.330s	24.156s	3.363ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	5.500s	19.063s	4.722ms	4	4	100.00
V2	target_mode_glitch	i2c_target_hrst	1.970s	23.065s	237.481us	3	3	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.250s	15.067s	7.481ms	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.240s	12.052s	583.141us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	16.015m	16.238m	27.794ms	5	5	100.00
		i2c_host_perf_precise	12.740s	17.195s	2.565ms	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	17.140s	25.213s	2.585ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	5.900s	27.080s	481.780us	3	3	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	3.060s	28.136s	518.107us	4	4	100.00
		i2c_target_nack_acqfull_addr	2.560s	27.136s	974.935us	5	5	100.00
		i2c_target_nack_txstretch	1.720s	26.143s	141.021us	2	3	66.67
V2	host_mode_halt_on_nak	i2c_host_may_nack	13.610s	39.132s	611.226us	10	10	100.00
V2	target_mode_n_byte_ack_control	target_mode_n_byte_ack_control				0	0	--
V2	target_mode_bus_timeout	target_mode_bus_timeout				0	0	--
V2	controller_mode_bus_timeout	controller_mode_bus_timeout				0	0	--
V2	controller_mode_bus_idle_delay	controller_mode_bus_idle_delay				0	0	--
V2	loopback_test	loopback_test				0	0	--
V2	multi_controller_clock_synchronization	multi_controller_clock_synchronization				0	0	--
V2	multi_controller_arbitration_lost_interference	multi_controller_arbitration_lost_interference				0	0	--
V2	multi_controller_arbitration_lost	multi_controller_arbitration_lost				0	0	--
V2	target_mode_arbitration_lost_interference	target_mode_arbitration_lost_interference				0	0	--
V2	target_mode_arbitration_lost	target_mode_arbitration_lost				0	0	--
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	1.970s	15.063s	456.062us	1	1	100.00
V2	alert_test	i2c_alert_test	0.800s	19.138s	16.220us	3	3	100.00
V2	intr_test	i2c_intr_test	0.810s	8.150s	84.916us	7	7	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	1.330s	10.088s	506.423us	4	4	100.00
V2	tl_d_illegal_access	i2c_tl_errors	1.330s	10.088s	506.423us	4	4	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.610s	9.155s	27.196us	5	5	100.00
		i2c_csr_rw	6.370s	14.133s	10.721ms	5	5	100.00
		i2c_csr_aliasing	1.190s	7.058s	92.811us	5	5	100.00
		i2c_same_csr_outstanding	0.880s	9.069s	49.187us	4	4	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.610s	9.155s	27.196us	5	5	100.00
		i2c_csr_rw	6.370s	14.133s	10.721ms	5	5	100.00
		i2c_csr_aliasing	1.190s	7.058s	92.811us	5	5	100.00
		i2c_same_csr_outstanding	0.880s	9.069s	49.187us	4	4	100.00
V2		TOTAL				113	121	93.39
V2S	tl_intg_err	i2c_tl_intg_err	1.590s	9.080s	128.870us	7	7	100.00
		i2c_sec_cm	1.140s	22.126s	328.375us	3	3	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.590s	9.080s	128.870us	7	7	100.00
V2S		TOTAL				10	10	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	34.170s	1.105m	896.706us	0	10	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.280s	5.046s	378.532us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	23.990s	45.166s	4.180ms	0	10	0.00
V3	target_loopback					0	0	--
V3		TOTAL				0	21	0.00
		TOTAL				152	181	83.98

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	49	38	33	67.35
V2S	2	2	2	100.00
V3	4	3	0	0.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
83.97	97.25	89.21	73.65	47.62	93.83	96.41	89.85

Simulation Wall Clock Time

Target	Elapsed
build	00:07:13
run	30:46:43
cov_merge	30:47:37
cov_report	30:47:52
Total	30:47:52

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:1237) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 18 failures:

Test i2c_host_stress_all_with_rand_reset has 10 failures.

0.i2c_host_stress_all_with_rand_reset.113913361712904017296940526876508146300573585718811659261785298059589076358022
Line 102, in log /home/runner/_work/pavona/pavona/scratch/main/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1989095579 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1989095579 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_stress_all_with_rand_reset.46966178605827739191699230184917509749666303489582699639068284091588668226072
Line 104, in log /home/runner/_work/pavona/pavona/scratch/main/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2633527883 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2633527883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test i2c_target_stress_all_with_rand_reset has 8 failures.

0.i2c_target_stress_all_with_rand_reset.33110211479595956358671027596067998192253897841551045310416079705390908923407
Line 95, in log /home/runner/_work/pavona/pavona/scratch/main/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 507602569 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 507602569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_target_stress_all_with_rand_reset.34528486528492583518566710463931415805485311352988817323846142638314022323110
Line 95, in log /home/runner/_work/pavona/pavona/scratch/main/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1342355248 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1342355248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 6 failures:

Test i2c_host_error_intr has 2 failures.

3.i2c_host_error_intr.67292036131148717710036624077963793717854620637300475882715633491180664642859
Line 93, in log /home/runner/_work/pavona/pavona/scratch/main/i2c-sim-vcs/3.i2c_host_error_intr/latest/run.log

  UVM_ERROR @  70433472 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @  70433472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.i2c_host_error_intr.26945387199888512065275479672350978466312757166807978656691329262736560661862
Line 93, in log /home/runner/_work/pavona/pavona/scratch/main/i2c-sim-vcs/4.i2c_host_error_intr/latest/run.log

  UVM_ERROR @  52520825 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @  52520825 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test i2c_target_stress_all_with_rand_reset has 2 failures.

3.i2c_target_stress_all_with_rand_reset.87570631972448114427115073715522310616903327145639882254705859898097155899945
Line 97, in log /home/runner/_work/pavona/pavona/scratch/main/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2471694308 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 2471694308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.i2c_target_stress_all_with_rand_reset.20905500552303610753212811513320444870950085862814986308628366083234738835055
Line 111, in log /home/runner/_work/pavona/pavona/scratch/main/i2c-sim-vcs/9.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 162338535 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 162338535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test i2c_host_mode_toggle has 1 failures.

3.i2c_host_mode_toggle.57237201913718316348284657090401180885241970880188004089991314979382540910271
Line 88, in log /home/runner/_work/pavona/pavona/scratch/main/i2c-sim-vcs/3.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  14251748 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @  14251748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test i2c_host_stress_all has 1 failures.

4.i2c_host_stress_all.68801776858541400529011844590885035762968280590917111498313343637199802513567
Line 201, in log /home/runner/_work/pavona/pavona/scratch/main/i2c-sim-vcs/4.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 20624964602 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 20624964602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 2 failures:

Test i2c_target_glitch has 2 failures.

0.i2c_target_glitch.25346839202937058190664834757389439560994370691050628565204341687582677386658
Line 86, in log /home/runner/_work/pavona/pavona/scratch/main/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

  UVM_ERROR @ 537273450 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
  UVM_INFO @ 537273450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_target_glitch.111430004912276913145883527560292506529975324747895339635619438812339908708617
Line 91, in log /home/runner/_work/pavona/pavona/scratch/main/i2c-sim-vcs/1.i2c_target_glitch/latest/run.log

  UVM_ERROR @ 548398919 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
  UVM_INFO @ 548398919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:
- Test i2c_target_unexp_stop has 1 failures.
  - 0.i2c_target_unexp_stop.14983588728679460795432986596293839582551106000064865390869031648828258470568
    Line 80, in log /home/runner/_work/pavona/pavona/scratch/main/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 378532126 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 155 [0x9b])
  UVM_INFO @ 378532126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 1 failures:
- Test i2c_target_nack_txstretch has 1 failures.
  - 2.i2c_target_nack_txstretch.18913795210740294834442056200768766603657751869501073054692491755168227668056
    Line 85, in log /home/runner/_work/pavona/pavona/scratch/main/i2c-sim-vcs/2.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 192712103 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 192712103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:
- Test i2c_host_mode_toggle has 1 failures.
  - 4.i2c_host_mode_toggle.69685386276470365651016808757653608975008722015557946208385715879768455227635
    Line 86, in log /home/runner/_work/pavona/pavona/scratch/main/i2c-sim-vcs/4.i2c_host_mode_toggle/latest/run.log
```
  UVM_FATAL @  64697861 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=0xbeb0e594, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @  64697861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```