KEYMGR Simulation Results

Sunday August 02 2026 00:03:30 UTC

GitHub Revision: 0ff052588e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	2.560s	15.247s	331.865us	1	1	100.00
V1	random	keymgr_random	46.010s	55.732s	6.012ms	5	5	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.250s	10.096s	166.750us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.050s	10.097s	26.416us	3	3	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	14.550s	23.271s	885.026us	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	6.180s	16.131s	438.314us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	1.690s	11.169s	40.844us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.050s	10.097s	26.416us	3	3	100.00
		keymgr_csr_aliasing	6.180s	16.131s	438.314us	5	5	100.00
V1		TOTAL				44	44	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	1.121m	1.300m	14.470ms	24	24	100.00
V2	sideload	keymgr_sideload	1.760s	16.258s	134.089us	1	1	100.00
		keymgr_sideload_kmac	2.080s	17.211s	151.458us	3	3	100.00
		keymgr_sideload_aes	1.940s	20.216s	40.202us	1	1	100.00
		keymgr_sideload_acc	3.260s	17.210s	310.023us	3	3	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	1.320s	16.179s	75.379us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	23.270s	32.388s	793.898us	12	12	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	3.110s	16.167s	213.743us	13	14	92.86
V2	invalid_sw_input	keymgr_sw_invalid_input	16.460s	29.356s	2.356ms	7	7	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	23.460s	36.386s	12.199ms	13	13	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	4.830s	18.166s	318.761us	4	4	100.00
V2	stress_all	keymgr_stress_all	3.549m	3.615m	146.709ms	25	25	100.00
V2	intr_test	keymgr_intr_test	0.930s	11.146s	48.763us	50	50	100.00
V2	alert_test	keymgr_alert_test	0.920s	11.125s	83.238us	3	3	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	2.880s	11.133s	241.538us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	2.880s	11.133s	241.538us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.250s	10.096s	166.750us	5	5	100.00
		keymgr_csr_rw	1.050s	10.097s	26.416us	3	3	100.00
		keymgr_csr_aliasing	6.180s	16.131s	438.314us	5	5	100.00
		keymgr_same_csr_outstanding	2.930s	16.173s	220.386us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.250s	10.096s	166.750us	5	5	100.00
		keymgr_csr_rw	1.050s	10.097s	26.416us	3	3	100.00
		keymgr_csr_aliasing	6.180s	16.131s	438.314us	5	5	100.00
		keymgr_same_csr_outstanding	2.930s	16.173s	220.386us	20	20	100.00
V2		TOTAL				200	201	99.50
V2S	sec_cm_additional_check	keymgr_sec_cm	8.320s	17.178s	1.586ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	8.320s	17.178s	1.586ms	5	5	100.00
		keymgr_tl_intg_err	5.510s	14.120s	910.993us	19	19	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	2.990s	10.073s	329.567us	3	3	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	2.990s	10.073s	329.567us	3	3	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	2.990s	10.073s	329.567us	3	3	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	2.990s	10.073s	329.567us	3	3	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	5.270s	18.198s	237.706us	4	4	100.00
V2S	prim_count_check	keymgr_sec_cm	8.320s	17.178s	1.586ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	8.320s	17.178s	1.586ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	5.510s	14.120s	910.993us	19	19	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	2.990s	10.073s	329.567us	3	3	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.121m	1.300m	14.470ms	24	24	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	46.010s	55.732s	6.012ms	5	5	100.00
		keymgr_csr_rw	1.050s	10.097s	26.416us	3	3	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	46.010s	55.732s	6.012ms	5	5	100.00
		keymgr_csr_rw	1.050s	10.097s	26.416us	3	3	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	46.010s	55.732s	6.012ms	5	5	100.00
		keymgr_csr_rw	1.050s	10.097s	26.416us	3	3	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	23.270s	32.388s	793.898us	12	12	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	23.460s	36.386s	12.199ms	13	13	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	23.460s	36.386s	12.199ms	13	13	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	46.010s	55.732s	6.012ms	5	5	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	1.610s	14.108s	41.262us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	8.320s	17.178s	1.586ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	8.320s	17.178s	1.586ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	8.320s	17.178s	1.586ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	3.960s	28.222s	2.562ms	28	28	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	23.270s	32.388s	793.898us	12	12	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	8.320s	17.178s	1.586ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	8.320s	17.178s	1.586ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	8.320s	17.178s	1.586ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	3.960s	28.222s	2.562ms	28	28	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	3.960s	28.222s	2.562ms	28	28	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	8.320s	17.178s	1.586ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	3.960s	28.222s	2.562ms	28	28	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	8.320s	17.178s	1.586ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	3.960s	28.222s	2.562ms	28	28	100.00
V2S		TOTAL				60	60	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	13.570s	23.305s	1.064ms	13	14	92.86
V3		TOTAL				13	14	92.86
		TOTAL				317	319	99.37

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	16	16	15	93.75
V2S	6	6	6	100.00
V3	1	1	0	0.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.63	99.21	98.22	98.01	100.00	99.01	97.72	91.23

Simulation Wall Clock Time

Target	Elapsed
build	00:07:13
run	30:46:43
cov_merge	30:47:37
cov_report	30:47:52
Total	30:47:52

Failure Buckets

• UVM_ERROR (cip_base_scoreboard.sv:271) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_operation_err triggered unexpectedly has 1 failures:

  • Test keymgr_kmac_rsp_err has 1 failures.

    • 8.keymgr_kmac_rsp_err.103920028486636199059614871658040952625441648427679982700118822797736299106003
      Line 259, in log /home/runner/_work/pavona/pavona/scratch/main/keymgr-sim-vcs/8.keymgr_kmac_rsp_err/latest/run.log

        UVM_ERROR @  19548139 ps: (cip_base_scoreboard.sv:271) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_operation_err triggered unexpectedly
        UVM_INFO @  19548139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1237) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test keymgr_stress_all_with_rand_reset has 1 failures.

    • 13.keymgr_stress_all_with_rand_reset.54178063131814184475544780836214294218513686922478365878415346764106407064263
      Line 140, in log /home/runner/_work/pavona/pavona/scratch/main/keymgr-sim-vcs/13.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 158171093 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 158171093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---