KEYMGR_DPE Simulation Results

Sunday August 02 2026 00:03:30 UTC

GitHub Revision: 0ff052588e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_dpe_smoke	36.560s	54.717s	8.091ms	32	32	100.00
V1	csr_hw_reset	keymgr_dpe_csr_hw_reset	1.100s	13.613s	54.138us	5	5	100.00
V1	csr_rw	keymgr_dpe_csr_rw	1.120s	12.563s	74.513us	20	20	100.00
V1	csr_bit_bash	keymgr_dpe_csr_bit_bash	6.170s	15.716s	3.340ms	5	5	100.00
V1	csr_aliasing	keymgr_dpe_csr_aliasing	5.220s	13.187s	1.115ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_dpe_csr_mem_rw_with_rand_reset	1.520s	10.412s	56.363us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_dpe_csr_rw	1.120s	12.563s	74.513us	20	20	100.00
		keymgr_dpe_csr_aliasing	5.220s	13.187s	1.115ms	5	5	100.00
V1		TOTAL				87	87	100.00
V2	intr_test	keymgr_dpe_intr_test	0.930s	13.645s	17.141us	5	5	100.00
V2	alert_test	keymgr_dpe_alert_test	0.760s	14.148s	97.385us	3	3	100.00
V2	tl_d_oob_addr_access	keymgr_dpe_tl_errors	2.530s	23.760s	153.467us	5	5	100.00
V2	tl_d_illegal_access	keymgr_dpe_tl_errors	2.530s	23.760s	153.467us	5	5	100.00
V2	tl_d_outstanding_access	keymgr_dpe_csr_hw_reset	1.100s	13.613s	54.138us	5	5	100.00
		keymgr_dpe_csr_rw	1.120s	12.563s	74.513us	20	20	100.00
		keymgr_dpe_csr_aliasing	5.220s	13.187s	1.115ms	5	5	100.00
		keymgr_dpe_same_csr_outstanding	2.260s	11.470s	98.930us	3	3	100.00
V2	tl_d_partial_access	keymgr_dpe_csr_hw_reset	1.100s	13.613s	54.138us	5	5	100.00
		keymgr_dpe_csr_rw	1.120s	12.563s	74.513us	20	20	100.00
		keymgr_dpe_csr_aliasing	5.220s	13.187s	1.115ms	5	5	100.00
		keymgr_dpe_same_csr_outstanding	2.260s	11.470s	98.930us	3	3	100.00
V2		TOTAL				16	16	100.00
V2S	tl_intg_err	keymgr_dpe_sec_cm	17.870s	23.433s	1.179ms	5	5	100.00
		keymgr_dpe_tl_intg_err	5.590s	17.709s	756.037us	17	17	100.00
V2S	shadow_reg_update_error	keymgr_dpe_shadow_reg_errors	2.220s	20.485s	475.961us	3	3	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_dpe_shadow_reg_errors	2.220s	20.485s	475.961us	3	3	100.00
V2S	shadow_reg_storage_error	keymgr_dpe_shadow_reg_errors	2.220s	20.485s	475.961us	3	3	100.00
V2S	shadowed_reset_glitch	keymgr_dpe_shadow_reg_errors	2.220s	20.485s	475.961us	3	3	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_dpe_shadow_reg_errors_with_csr_rw	4.710s	22.677s	892.775us	3	3	100.00
V2S	prim_count_check	keymgr_dpe_sec_cm	17.870s	23.433s	1.179ms	5	5	100.00
V2S	prim_fsm_check	keymgr_dpe_sec_cm	17.870s	23.433s	1.179ms	5	5	100.00
V2S		TOTAL				28	28	100.00
V3	stress_all_with_rand_reset	keymgr_dpe_stress_all_with_rand_reset				0	0	--
V3		TOTAL				0	0	--
		TOTAL				131	131	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	4	4	4	100.00
V2S	4	4	4	100.00
V3	1	0	0	0.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
76.55	97.70	90.39	62.37	75.68	94.61	97.64	17.46

Simulation Wall Clock Time

Target	Elapsed
build	00:07:13
run	30:46:43
cov_merge	30:47:37
cov_report	30:47:52
Total	30:47:52