KMAC/MASKED Simulation Results

Sunday August 02 2026 00:03:30 UTC

GitHub Revision: 0ff052588e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Max Wall Clock Simulated Time Passing Total Pass Rate
V1 smoke kmac_smoke 48.540s 2.036m 8.219ms 3 3 100.00
V1 csr_hw_reset kmac_csr_hw_reset 0.730s 16.073s 66.093us 5 5 100.00
V1 csr_rw kmac_csr_rw 0.870s 16.107s 144.313us 20 20 100.00
V1 csr_bit_bash kmac_csr_bit_bash 7.950s 19.108s 1.765ms 5 5 100.00
V1 csr_aliasing kmac_csr_aliasing 4.770s 18.099s 1.028ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset kmac_csr_mem_rw_with_rand_reset 1.560s 14.093s 151.735us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr kmac_csr_rw 0.870s 16.107s 144.313us 20 20 100.00
kmac_csr_aliasing 4.770s 18.099s 1.028ms 5 5 100.00
V1 mem_walk kmac_mem_walk 0.600s 14.075s 42.100us 5 5 100.00
V1 mem_partial_access kmac_mem_partial_access 1.030s 14.097s 46.320us 5 5 100.00
V1 TOTAL 68 68 100.00
V2 long_msg_and_output kmac_long_msg_and_output 27.192m 27.500m 87.942ms 1 1 100.00
V2 burst_write kmac_burst_write 5.413m 5.765m 10.010ms 1 1 100.00
V2 test_vectors kmac_test_vectors_sha3_224 29.157m 30.629m 62.149ms 5 5 100.00
kmac_test_vectors_sha3_256 30.137m 31.064m 540.458ms 5 5 100.00
kmac_test_vectors_sha3_384 27.561m 30.141m 548.698ms 5 5 100.00
kmac_test_vectors_sha3_512 15.545m 16.706m 88.935ms 5 5 100.00
kmac_test_vectors_shake_128 41.645m 44.397m 117.023ms 5 5 100.00
kmac_test_vectors_shake_256 5.029m 5.714m 98.362ms 3 3 100.00
kmac_test_vectors_kmac 2.870s 2.952m 125.353us 5 5 100.00
kmac_test_vectors_kmac_xof 2.200s 2.936m 85.849us 5 5 100.00
V2 sideload kmac_sideload 1.734m 2.092m 5.111ms 1 1 100.00
V2 app kmac_app 4.096m 5.095m 29.102ms 3 3 100.00
V2 app_with_partial_data kmac_app_with_partial_data 3.277m 4.275m 9.710ms 4 4 100.00
V2 entropy_refresh kmac_entropy_refresh 4.445m 5.588m 79.935ms 5 5 100.00
V2 error kmac_error 5.607m 6.964m 112.925ms 4 4 100.00
V2 key_error kmac_key_error 7.700s 1.620m 6.892ms 3 3 100.00
V2 sideload_invalid kmac_sideload_invalid 5.820s 2.485m 217.144us 5 5 100.00
V2 edn_timeout_error kmac_edn_timeout_error 21.180s 1.803m 4.860ms 3 3 100.00
V2 entropy_mode_error kmac_entropy_mode_error 1.300s 1.887m 84.228us 3 3 100.00
V2 entropy_ready_error kmac_entropy_ready_error 21.770s 2.088m 2.815ms 3 3 100.00
V2 lc_escalation kmac_lc_escalation 31.710s 3.185m 790.165us 13 13 100.00
V2 stress_all kmac_stress_all 35.782m 37.307m 98.976ms 4 4 100.00
V2 intr_test kmac_intr_test 0.620s 14.095s 52.664us 5 5 100.00
V2 alert_test kmac_alert_test 1.050s 2.320m 48.756us 3 3 100.00
V2 tl_d_oob_addr_access kmac_tl_errors 2.250s 15.106s 653.550us 20 20 100.00
V2 tl_d_illegal_access kmac_tl_errors 2.250s 15.106s 653.550us 20 20 100.00
V2 tl_d_outstanding_access kmac_csr_hw_reset 0.730s 16.073s 66.093us 5 5 100.00
kmac_csr_rw 0.870s 16.107s 144.313us 20 20 100.00
kmac_csr_aliasing 4.770s 18.099s 1.028ms 5 5 100.00
kmac_same_csr_outstanding 1.780s 15.071s 439.720us 20 20 100.00
V2 tl_d_partial_access kmac_csr_hw_reset 0.730s 16.073s 66.093us 5 5 100.00
kmac_csr_rw 0.870s 16.107s 144.313us 20 20 100.00
kmac_csr_aliasing 4.770s 18.099s 1.028ms 5 5 100.00
kmac_same_csr_outstanding 1.780s 15.071s 439.720us 20 20 100.00
V2 TOTAL 139 139 100.00
V2S shadow_reg_update_error kmac_shadow_reg_errors 1.230s 14.100s 145.381us 3 3 100.00
V2S shadow_reg_read_clear_staged_value kmac_shadow_reg_errors 1.230s 14.100s 145.381us 3 3 100.00
V2S shadow_reg_storage_error kmac_shadow_reg_errors 1.230s 14.100s 145.381us 3 3 100.00
V2S shadowed_reset_glitch kmac_shadow_reg_errors 1.230s 14.100s 145.381us 3 3 100.00
V2S shadow_reg_update_error_with_csr_rw kmac_shadow_reg_errors_with_csr_rw 2.840s 16.112s 862.037us 4 4 100.00
V2S tl_intg_err kmac_sec_cm 1.551m 4.720m 34.429ms 5 5 100.00
kmac_tl_intg_err 2.940s 16.111s 903.253us 6 6 100.00
V2S sec_cm_bus_integrity kmac_tl_intg_err 2.940s 16.111s 903.253us 6 6 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi kmac_lc_escalation 31.710s 3.185m 790.165us 13 13 100.00
V2S sec_cm_sw_key_key_masking kmac_smoke 48.540s 2.036m 8.219ms 3 3 100.00
V2S sec_cm_key_sideload kmac_sideload 1.734m 2.092m 5.111ms 1 1 100.00
V2S sec_cm_cfg_shadowed_config_shadow kmac_shadow_reg_errors 1.230s 14.100s 145.381us 3 3 100.00
V2S sec_cm_fsm_sparse kmac_sec_cm 1.551m 4.720m 34.429ms 5 5 100.00
V2S sec_cm_ctr_redun kmac_sec_cm 1.551m 4.720m 34.429ms 5 5 100.00
V2S sec_cm_packer_ctr_redun kmac_sec_cm 1.551m 4.720m 34.429ms 5 5 100.00
V2S sec_cm_cfg_shadowed_config_regwen kmac_smoke 48.540s 2.036m 8.219ms 3 3 100.00
V2S sec_cm_fsm_global_esc kmac_lc_escalation 31.710s 3.185m 790.165us 13 13 100.00
V2S sec_cm_fsm_local_esc kmac_sec_cm 1.551m 4.720m 34.429ms 5 5 100.00
V2S sec_cm_absorbed_ctrl_mubi kmac_mubi 4.786m 6.339m 98.932ms 10 10 100.00
V2S sec_cm_sw_cmd_ctrl_sparse kmac_smoke 48.540s 2.036m 8.219ms 3 3 100.00
V2S TOTAL 28 28 100.00
V3 throughput kmac_throughput 0 0 --
V3 stress_all_with_rand_reset kmac_stress_all_with_rand_reset 2.086m 3.041m 14.076ms 4 4 100.00
V3 TOTAL 4 4 100.00
TOTAL 239 239 100.00

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 26 26 26 100.00
V2S 5 5 5 100.00
V3 2 1 1 50.00

Coverage Results

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
93.73 98.96 94.12 95.53 76.10 96.15 97.74 97.52

Simulation Wall Clock Time

Target Elapsed
build 00:07:13
run 30:46:43
cov_merge 30:47:37
cov_report 30:47:52
Total 30:47:52