KMAC/UNMASKED Simulation Results

Sunday August 02 2026 00:03:30 UTC

GitHub Revision: 0ff052588e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	13.550s	17.319s	8.143ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	0.740s	5.071s	110.446us	5	5	100.00
V1	csr_rw	kmac_csr_rw	0.720s	5.070s	33.489us	3	3	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	9.980s	14.164s	4.147ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	4.670s	9.101s	1.227ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	1.230s	6.067s	45.860us	3	3	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	0.720s	5.070s	33.489us	3	3	100.00
		kmac_csr_aliasing	4.670s	9.101s	1.227ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.550s	5.070s	16.384us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	0.940s	6.059s	178.153us	5	5	100.00
V1		TOTAL				32	32	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	17.455m	17.537m	343.080ms	1	1	100.00
V2	burst_write	kmac_burst_write	2.749m	2.826m	33.929ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	16.835m	17.832m	74.847ms	3	3	100.00
		kmac_test_vectors_sha3_256	31.250s	2.002m	4.369ms	5	5	100.00
		kmac_test_vectors_sha3_384	16.169m	16.748m	46.695ms	5	5	100.00
		kmac_test_vectors_sha3_512	11.747m	11.822m	158.018ms	5	5	100.00
		kmac_test_vectors_shake_128	27.707m	29.140m	71.134ms	5	5	100.00
		kmac_test_vectors_shake_256	24.485m	25.233m	273.283ms	5	5	100.00
		kmac_test_vectors_kmac	2.230s	36.101s	623.279us	5	5	100.00
		kmac_test_vectors_kmac_xof	2.420s	38.106s	361.187us	5	5	100.00
V2	sideload	kmac_sideload	1.361m	1.424m	2.092ms	1	1	100.00
V2	app	kmac_app	3.143m	3.623m	54.505ms	5	5	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	3.438m	4.004m	26.425ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	1.953m	2.022m	11.261ms	3	3	100.00
V2	error	kmac_error	3.174m	3.737m	4.535ms	6	6	100.00
V2	key_error	kmac_key_error	5.710s	49.081s	3.258ms	3	3	100.00
V2	sideload_invalid	kmac_sideload_invalid	2.960s	1.035m	257.480us	4	4	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	30.150s	2.102m	5.726ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	35.970s	2.318m	2.015ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	31.000s	1.302m	4.525ms	3	3	100.00
V2	lc_escalation	kmac_lc_escalation	12.360s	2.001m	1.228ms	10	10	100.00
V2	stress_all	kmac_stress_all	25.958m	26.751m	346.466ms	5	5	100.00
V2	intr_test	kmac_intr_test	0.570s	5.069s	16.700us	5	5	100.00
V2	alert_test	kmac_alert_test	0.940s	1.069m	15.774us	3	3	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.390s	9.086s	394.377us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.390s	9.086s	394.377us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	0.740s	5.071s	110.446us	5	5	100.00
		kmac_csr_rw	0.720s	5.070s	33.489us	3	3	100.00
		kmac_csr_aliasing	4.670s	9.101s	1.227ms	5	5	100.00
		kmac_same_csr_outstanding	1.530s	8.077s	125.866us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	0.740s	5.071s	110.446us	5	5	100.00
		kmac_csr_rw	0.720s	5.070s	33.489us	3	3	100.00
		kmac_csr_aliasing	4.670s	9.101s	1.227ms	5	5	100.00
		kmac_same_csr_outstanding	1.530s	8.077s	125.866us	20	20	100.00
V2		TOTAL				178	178	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.220s	5.073s	318.193us	3	3	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.220s	5.073s	318.193us	3	3	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.220s	5.073s	318.193us	3	3	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.220s	5.073s	318.193us	3	3	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.850s	7.089s	504.630us	5	5	100.00
V2S	tl_intg_err	kmac_sec_cm	39.350s	1.469m	10.699ms	3	3	100.00
		kmac_tl_intg_err	2.630s	7.093s	438.490us	8	8	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	2.630s	7.093s	438.490us	8	8	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	12.360s	2.001m	1.228ms	10	10	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	13.550s	17.319s	8.143ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	1.361m	1.424m	2.092ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.220s	5.073s	318.193us	3	3	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	39.350s	1.469m	10.699ms	3	3	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	39.350s	1.469m	10.699ms	3	3	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	39.350s	1.469m	10.699ms	3	3	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	13.550s	17.319s	8.143ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	12.360s	2.001m	1.228ms	10	10	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	39.350s	1.469m	10.699ms	3	3	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	2.406m	4.272m	4.359ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	13.550s	17.319s	8.143ms	1	1	100.00
V2S		TOTAL				29	29	100.00
V3	throughput	kmac_throughput				0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.131m	2.654m	4.591ms	2	4	50.00
V3		TOTAL				2	4	50.00
		TOTAL				241	243	99.18

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	26	26	26	100.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.64	97.28	94.06	99.78	68.84	94.84	97.56	96.11

Simulation Wall Clock Time

Target	Elapsed
build	00:07:13
run	30:46:43
cov_merge	30:47:37
cov_report	30:47:52
Total	30:47:52

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:1237) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
  • Test kmac_stress_all_with_rand_reset has 2 failures.

    • 1.kmac_stress_all_with_rand_reset.34448193940038164736077802001109796537616269344824909254614357678388362702929
      Line 149, in log /home/runner/_work/pavona/pavona/scratch/main/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 14067268812 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 14067268812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.kmac_stress_all_with_rand_reset.18134520465270645152263816686571560650187915683241591830094983543971052516455
      Line 107, in log /home/runner/_work/pavona/pavona/scratch/main/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2962364187 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2962364187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---