LC_CTRL/DMI_VOLATILE_UNLOCK_DISABLED Simulation Results

Sunday August 02 2026 00:03:30 UTC

GitHub Revision: 0ff052588e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Max Wall Clock Simulated Time Passing Total Pass Rate
V1 smoke lc_ctrl_smoke 1.190s 6.126s 178.374us 1 1 100.00
V1 csr_hw_reset lc_ctrl_csr_hw_reset 1.110s 11.351s 17.299us 5 5 100.00
V1 csr_rw lc_ctrl_csr_rw 1.010s 10.288s 14.361us 3 3 100.00
V1 csr_bit_bash lc_ctrl_csr_bit_bash 1.970s 12.348s 401.343us 5 5 100.00
V1 csr_aliasing lc_ctrl_csr_aliasing 1.340s 10.342s 64.543us 5 5 100.00
V1 csr_mem_rw_with_rand_reset lc_ctrl_csr_mem_rw_with_rand_reset 1.250s 10.457s 86.392us 3 3 100.00
V1 regwen_csr_and_corresponding_lockable_csr lc_ctrl_csr_rw 1.010s 10.288s 14.361us 3 3 100.00
lc_ctrl_csr_aliasing 1.340s 10.342s 64.543us 5 5 100.00
V1 TOTAL 22 22 100.00
V2 state_post_trans lc_ctrl_state_post_trans 4.230s 8.134s 87.502us 1 1 100.00
V2 regwen_during_op lc_ctrl_regwen_during_op 11.500s 32.137s 860.605us 10 10 100.00
V2 rand_wr_claim_transition_if lc_ctrl_claim_transition_if 1.090s 30.084s 12.540us 10 10 100.00
V2 lc_prog_failure lc_ctrl_prog_failure 1.200s 5.097s 436.046us 1 1 100.00
V2 lc_state_failure lc_ctrl_state_failure 6.450s 10.174s 929.816us 1 1 100.00
V2 lc_errors lc_ctrl_errors 3.310s 7.124s 236.198us 1 1 100.00
V2 security_escalation lc_ctrl_state_failure 6.450s 10.174s 929.816us 1 1 100.00
lc_ctrl_prog_failure 1.200s 5.097s 436.046us 1 1 100.00
lc_ctrl_errors 3.310s 7.124s 236.198us 1 1 100.00
lc_ctrl_security_escalation 7.560s 21.652s 967.838us 5 5 100.00
lc_ctrl_jtag_state_failure 50.780s 1.094m 3.430ms 20 20 100.00
lc_ctrl_jtag_prog_failure 7.300s 17.632s 1.033ms 3 3 100.00
lc_ctrl_jtag_errors 1.076m 1.297m 17.445ms 20 20 100.00
V2 jtag_access lc_ctrl_jtag_smoke 7.550s 16.503s 1.860ms 3 3 100.00
lc_ctrl_jtag_state_post_trans 12.460s 17.543s 2.711ms 3 3 100.00
lc_ctrl_jtag_prog_failure 7.300s 17.632s 1.033ms 3 3 100.00
lc_ctrl_jtag_errors 1.076m 1.297m 17.445ms 20 20 100.00
lc_ctrl_jtag_access 2.690s 13.469s 292.939us 3 3 100.00
lc_ctrl_jtag_regwen_during_op 21.230s 39.710s 5.178ms 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 1.920s 13.359s 163.555us 3 3 100.00
lc_ctrl_jtag_csr_rw 2.640s 17.467s 101.852us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 15.050s 21.648s 6.393ms 10 10 100.00
lc_ctrl_jtag_csr_aliasing 15.530s 19.425s 5.075ms 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 1.400s 12.329s 92.214us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.800s 13.426s 625.514us 10 10 100.00
lc_ctrl_jtag_alert_test 2.440s 14.414s 184.145us 10 10 100.00
V2 jtag_priority lc_ctrl_jtag_priority 6.730s 31.808s 2.457ms 10 10 100.00
V2 lc_ctrl_volatile_unlock lc_ctrl_volatile_unlock_smoke 1.100s 6.158s 20.020us 3 3 100.00
V2 stress_all lc_ctrl_stress_all 2.504m 2.858m 31.188ms 7 7 100.00
V2 alert_test lc_ctrl_alert_test 1.100s 11.294s 43.145us 3 3 100.00
V2 tl_d_oob_addr_access lc_ctrl_tl_errors 2.640s 12.324s 58.680us 3 3 100.00
V2 tl_d_illegal_access lc_ctrl_tl_errors 2.640s 12.324s 58.680us 3 3 100.00
V2 tl_d_outstanding_access lc_ctrl_csr_hw_reset 1.110s 11.351s 17.299us 5 5 100.00
lc_ctrl_csr_rw 1.010s 10.288s 14.361us 3 3 100.00
lc_ctrl_csr_aliasing 1.340s 10.342s 64.543us 5 5 100.00
lc_ctrl_same_csr_outstanding 1.180s 10.341s 156.478us 20 20 100.00
V2 tl_d_partial_access lc_ctrl_csr_hw_reset 1.110s 11.351s 17.299us 5 5 100.00
lc_ctrl_csr_rw 1.010s 10.288s 14.361us 3 3 100.00
lc_ctrl_csr_aliasing 1.340s 10.342s 64.543us 5 5 100.00
lc_ctrl_same_csr_outstanding 1.180s 10.341s 156.478us 20 20 100.00
V2 TOTAL 200 200 100.00
V2S tl_intg_err lc_ctrl_sec_cm 7.710s 16.593s 425.147us 3 3 100.00
lc_ctrl_tl_intg_err 2.820s 15.414s 143.496us 20 20 100.00
V2S sec_cm_bus_integrity lc_ctrl_tl_intg_err 2.820s 15.414s 143.496us 20 20 100.00
V2S sec_cm_transition_config_regwen lc_ctrl_regwen_during_op 11.500s 32.137s 860.605us 10 10 100.00
V2S sec_cm_manuf_state_sparse lc_ctrl_state_failure 6.450s 10.174s 929.816us 1 1 100.00
lc_ctrl_sec_cm 7.710s 16.593s 425.147us 3 3 100.00
V2S sec_cm_transition_ctr_sparse lc_ctrl_state_failure 6.450s 10.174s 929.816us 1 1 100.00
lc_ctrl_sec_cm 7.710s 16.593s 425.147us 3 3 100.00
V2S sec_cm_manuf_state_bkgn_chk lc_ctrl_state_failure 6.450s 10.174s 929.816us 1 1 100.00
lc_ctrl_sec_cm 7.710s 16.593s 425.147us 3 3 100.00
V2S sec_cm_transition_ctr_bkgn_chk lc_ctrl_state_failure 6.450s 10.174s 929.816us 1 1 100.00
lc_ctrl_sec_cm 7.710s 16.593s 425.147us 3 3 100.00
V2S sec_cm_state_config_sparse lc_ctrl_state_failure 6.450s 10.174s 929.816us 1 1 100.00
lc_ctrl_sec_cm 7.710s 16.593s 425.147us 3 3 100.00
V2S sec_cm_main_fsm_sparse lc_ctrl_state_failure 6.450s 10.174s 929.816us 1 1 100.00
lc_ctrl_sec_cm 7.710s 16.593s 425.147us 3 3 100.00
V2S sec_cm_kmac_fsm_sparse lc_ctrl_state_failure 6.450s 10.174s 929.816us 1 1 100.00
lc_ctrl_sec_cm 7.710s 16.593s 425.147us 3 3 100.00
V2S sec_cm_main_fsm_local_esc lc_ctrl_state_failure 6.450s 10.174s 929.816us 1 1 100.00
lc_ctrl_sec_cm 7.710s 16.593s 425.147us 3 3 100.00
V2S sec_cm_main_fsm_global_esc lc_ctrl_security_escalation 7.560s 21.652s 967.838us 5 5 100.00
V2S sec_cm_main_ctrl_flow_consistency lc_ctrl_state_post_trans 4.230s 8.134s 87.502us 1 1 100.00
lc_ctrl_jtag_state_post_trans 12.460s 17.543s 2.711ms 3 3 100.00
V2S sec_cm_intersig_mubi lc_ctrl_sec_mubi 7.570s 16.359s 661.569us 4 4 100.00
V2S sec_cm_token_valid_ctrl_mubi lc_ctrl_sec_mubi 7.570s 16.359s 661.569us 4 4 100.00
V2S sec_cm_token_digest lc_ctrl_sec_token_digest 3.220s 8.146s 499.751us 1 1 100.00
V2S sec_cm_token_mux_ctrl_redun lc_ctrl_sec_token_mux 8.360s 17.588s 948.606us 3 3 100.00
V2S sec_cm_token_valid_mux_redun lc_ctrl_sec_token_mux 8.360s 17.588s 948.606us 3 3 100.00
V2S TOTAL 31 31 100.00
V3 stress_all_with_rand_reset lc_ctrl_stress_all_with_rand_reset 1.584m 1.802m 7.349ms 8 8 100.00
V3 TOTAL 8 8 100.00
TOTAL 261 261 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 27 27 27 100.00
V2S 5 5 5 100.00
V3 1 1 1 100.00

Coverage Results

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
94.37 97.90 82.95 90.03 100.00 96.99 96.13 96.58

Simulation Wall Clock Time

Target Elapsed
build 00:07:13
run 30:46:43
cov_merge 30:47:37
cov_report 30:47:52
Total 30:47:52