LC_CTRL/DMI_VOLATILE_UNLOCK_ENABLED Simulation Results

Sunday August 02 2026 00:03:30 UTC

GitHub Revision: 0ff052588e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	1.530s	10.068s	120.923us	1	1	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.280s	30.081s	31.302us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.040s	30.087s	44.240us	3	3	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.610s	30.086s	38.248us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.230s	30.085s	37.076us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.060s	26.083s	62.048us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.040s	30.087s	44.240us	3	3	100.00
		lc_ctrl_csr_aliasing	1.230s	30.085s	37.076us	5	5	100.00
V1		TOTAL				39	39	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	7.360s	16.140s	216.240us	1	1	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	12.660s	46.029s	1.272ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.060s	29.727s	14.250us	9	9	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	1.370s	10.074s	72.856us	1	1	100.00
V2	lc_state_failure	lc_ctrl_state_failure	9.830s	17.160s	671.781us	1	1	100.00
V2	lc_errors	lc_ctrl_errors	12.360s	27.479s	1.476ms	4	4	100.00
V2	security_escalation	lc_ctrl_state_failure	9.830s	17.160s	671.781us	1	1	100.00
		lc_ctrl_prog_failure	1.370s	10.074s	72.856us	1	1	100.00
		lc_ctrl_errors	12.360s	27.479s	1.476ms	4	4	100.00
		lc_ctrl_security_escalation	10.600s	41.731s	411.011us	7	7	100.00
		lc_ctrl_jtag_state_failure	52.410s	1.167m	14.123ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	14.380s	34.870s	1.604ms	20	20	100.00
		lc_ctrl_jtag_errors	45.760s	1.012m	17.974ms	4	4	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	5.520s	21.574s	529.442us	4	4	100.00
		lc_ctrl_jtag_state_post_trans	12.680s	30.688s	399.575us	3	3	100.00
		lc_ctrl_jtag_prog_failure	14.380s	34.870s	1.604ms	20	20	100.00
		lc_ctrl_jtag_errors	45.760s	1.012m	17.974ms	4	4	100.00
		lc_ctrl_jtag_access	2.790s	20.333s	1.343ms	3	3	100.00
		lc_ctrl_jtag_regwen_during_op	21.170s	42.335s	2.555ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.270s	1.152m	355.694us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.540s	1.136m	95.614us	3	3	100.00
		lc_ctrl_jtag_csr_bit_bash	14.920s	1.185m	2.424ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	22.390s	1.169m	1.333ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.790s	1.052m	94.994us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.420s	53.108s	438.323us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.580s	53.101s	213.929us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	9.730s	39.961s	1.526ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.100s	14.300s	14.335us	3	3	100.00
V2	stress_all	lc_ctrl_stress_all	2.036m	2.259m	29.077ms	6	7	85.71
V2	alert_test	lc_ctrl_alert_test	1.040s	19.374s	22.105us	3	3	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	2.600s	47.098s	107.571us	3	3	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	2.600s	47.098s	107.571us	3	3	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.280s	30.081s	31.302us	5	5	100.00
		lc_ctrl_csr_rw	1.040s	30.087s	44.240us	3	3	100.00
		lc_ctrl_csr_aliasing	1.230s	30.085s	37.076us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.660s	26.083s	48.642us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.280s	30.081s	31.302us	5	5	100.00
		lc_ctrl_csr_rw	1.040s	30.087s	44.240us	3	3	100.00
		lc_ctrl_csr_aliasing	1.230s	30.085s	37.076us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.660s	26.083s	48.642us	20	20	100.00
V2		TOTAL				205	206	99.51
V2S	tl_intg_err	lc_ctrl_sec_cm	8.840s	24.508s	1.143ms	3	3	100.00
		lc_ctrl_tl_intg_err	3.590s	46.101s	122.545us	17	17	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	3.590s	46.101s	122.545us	17	17	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	12.660s	46.029s	1.272ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	9.830s	17.160s	671.781us	1	1	100.00
		lc_ctrl_sec_cm	8.840s	24.508s	1.143ms	3	3	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	9.830s	17.160s	671.781us	1	1	100.00
		lc_ctrl_sec_cm	8.840s	24.508s	1.143ms	3	3	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	9.830s	17.160s	671.781us	1	1	100.00
		lc_ctrl_sec_cm	8.840s	24.508s	1.143ms	3	3	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	9.830s	17.160s	671.781us	1	1	100.00
		lc_ctrl_sec_cm	8.840s	24.508s	1.143ms	3	3	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	9.830s	17.160s	671.781us	1	1	100.00
		lc_ctrl_sec_cm	8.840s	24.508s	1.143ms	3	3	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	9.830s	17.160s	671.781us	1	1	100.00
		lc_ctrl_sec_cm	8.840s	24.508s	1.143ms	3	3	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	9.830s	17.160s	671.781us	1	1	100.00
		lc_ctrl_sec_cm	8.840s	24.508s	1.143ms	3	3	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	9.830s	17.160s	671.781us	1	1	100.00
		lc_ctrl_sec_cm	8.840s	24.508s	1.143ms	3	3	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	10.600s	41.731s	411.011us	7	7	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	7.360s	16.140s	216.240us	1	1	100.00
		lc_ctrl_jtag_state_post_trans	12.680s	30.688s	399.575us	3	3	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	8.920s	24.389s	1.259ms	3	3	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	8.920s	24.389s	1.259ms	3	3	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	7.020s	22.196s	416.123us	1	1	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	5.870s	21.254s	1.172ms	3	3	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	5.870s	21.254s	1.172ms	3	3	100.00
V2S		TOTAL				27	27	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.319m	1.508m	4.154ms	3	5	60.00
V3		TOTAL				3	5	60.00
		TOTAL				274	277	98.92

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.29	97.87	82.75	90.03	100.00	96.85	96.13	96.40

Simulation Wall Clock Time

Target	Elapsed
build	00:07:13
run	30:46:43
cov_merge	30:47:37
cov_report	30:47:52
Total	30:47:52

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:1237) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 2.lc_ctrl_stress_all_with_rand_reset.81139495151590515957890771182820094598554731118364642332738578842226985800256
      Line 2935, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_dmi_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 11599827826 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 11599827826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.lc_ctrl_stress_all_with_rand_reset.21438353397088848849002463404162915944138232678663848568621196404361018124441
      Line 5518, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_dmi_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3158331740 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3158331740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_stress_all has 1 failures.

    • 5.lc_ctrl_stress_all.114892079798905376830377260787984563476545464421567762551459360050290804427028
      Line 9551, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_dmi_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 10996151959 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 10996151959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---