LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Sunday August 02 2026 00:03:30 UTC

GitHub Revision: 0ff052588e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	4.850s	1.022m	148.608us	3	3	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	0.830s	29.336s	25.907us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	0.760s	29.336s	19.613us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.170s	22.307s	121.220us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	0.990s	21.299s	113.932us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.060s	22.240s	66.065us	3	3	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	0.760s	29.336s	19.613us	20	20	100.00
		lc_ctrl_csr_aliasing	0.990s	21.299s	113.932us	5	5	100.00
V1		TOTAL				41	41	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	1.680s	36.085s	45.702us	1	1	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	13.270s	1.308m	804.333us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.810s	1.174m	22.433us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	1.170s	37.128s	79.397us	1	1	100.00
V2	lc_state_failure	lc_ctrl_state_failure	7.540s	1.122m	605.329us	4	4	100.00
V2	lc_errors	lc_ctrl_errors	4.240s	43.144s	315.189us	1	1	100.00
V2	security_escalation	lc_ctrl_state_failure	7.540s	1.122m	605.329us	4	4	100.00
		lc_ctrl_prog_failure	1.170s	37.128s	79.397us	1	1	100.00
		lc_ctrl_errors	4.240s	43.144s	315.189us	1	1	100.00
		lc_ctrl_security_escalation	4.210s	1.121m	1.253ms	5	5	100.00
		lc_ctrl_jtag_state_failure	13.350s	1.172m	1.333ms	3	3	100.00
		lc_ctrl_jtag_prog_failure	4.940s	1.256m	611.620us	3	3	100.00
		lc_ctrl_jtag_errors	43.490s	1.731m	3.448ms	19	20	95.00
V2	jtag_access	lc_ctrl_jtag_smoke	4.120s	1.022m	2.558ms	4	4	100.00
		lc_ctrl_jtag_state_post_trans	19.570s	1.273m	4.016ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	4.940s	1.256m	611.620us	3	3	100.00
		lc_ctrl_jtag_errors	43.490s	1.731m	3.448ms	19	20	95.00
		lc_ctrl_jtag_access	8.930s	1.072m	2.758ms	3	3	100.00
		lc_ctrl_jtag_regwen_during_op	17.540s	1.359m	1.200ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	2.800s	34.408s	1.055ms	10	10	100.00
		lc_ctrl_jtag_csr_rw	1.580s	36.505s	231.188us	3	3	100.00
		lc_ctrl_jtag_csr_bit_bash	24.690s	43.538s	2.537ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	13.120s	40.522s	15.106ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.130s	35.403s	39.378us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	3.100s	36.417s	239.753us	10	10	100.00
		lc_ctrl_jtag_alert_test	1.270s	35.402s	117.314us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	16.630s	1.389m	6.849ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	0.720s	1.021m	118.773us	3	3	100.00
V2	stress_all	lc_ctrl_stress_all	3.063m	4.179m	12.376ms	6	6	100.00
V2	alert_test	lc_ctrl_alert_test	0.720s	1.056m	98.989us	3	3	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	1.550s	35.382s	90.059us	3	3	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	1.550s	35.382s	90.059us	3	3	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	0.830s	29.336s	25.907us	5	5	100.00
		lc_ctrl_csr_rw	0.760s	29.336s	19.613us	20	20	100.00
		lc_ctrl_csr_aliasing	0.990s	21.299s	113.932us	5	5	100.00
		lc_ctrl_same_csr_outstanding	0.980s	22.291s	28.982us	3	3	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	0.830s	29.336s	25.907us	5	5	100.00
		lc_ctrl_csr_rw	0.760s	29.336s	19.613us	20	20	100.00
		lc_ctrl_csr_aliasing	0.990s	21.299s	113.932us	5	5	100.00
		lc_ctrl_same_csr_outstanding	0.980s	22.291s	28.982us	3	3	100.00
V2		TOTAL				185	186	99.46
V2S	tl_intg_err	lc_ctrl_sec_cm	5.660s	1.173m	270.757us	3	3	100.00
		lc_ctrl_tl_intg_err	5.310s	36.384s	2.052ms	19	19	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	5.310s	36.384s	2.052ms	19	19	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	13.270s	1.308m	804.333us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	7.540s	1.122m	605.329us	4	4	100.00
		lc_ctrl_sec_cm	5.660s	1.173m	270.757us	3	3	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	7.540s	1.122m	605.329us	4	4	100.00
		lc_ctrl_sec_cm	5.660s	1.173m	270.757us	3	3	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	7.540s	1.122m	605.329us	4	4	100.00
		lc_ctrl_sec_cm	5.660s	1.173m	270.757us	3	3	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	7.540s	1.122m	605.329us	4	4	100.00
		lc_ctrl_sec_cm	5.660s	1.173m	270.757us	3	3	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	7.540s	1.122m	605.329us	4	4	100.00
		lc_ctrl_sec_cm	5.660s	1.173m	270.757us	3	3	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	7.540s	1.122m	605.329us	4	4	100.00
		lc_ctrl_sec_cm	5.660s	1.173m	270.757us	3	3	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	7.540s	1.122m	605.329us	4	4	100.00
		lc_ctrl_sec_cm	5.660s	1.173m	270.757us	3	3	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	7.540s	1.122m	605.329us	4	4	100.00
		lc_ctrl_sec_cm	5.660s	1.173m	270.757us	3	3	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	4.210s	1.121m	1.253ms	5	5	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	1.680s	36.085s	45.702us	1	1	100.00
		lc_ctrl_jtag_state_post_trans	19.570s	1.273m	4.016ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	7.180s	1.356m	8.990ms	4	4	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	7.180s	1.356m	8.990ms	4	4	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	4.940s	1.088m	269.898us	1	1	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	4.470s	1.339m	1.016ms	3	3	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	4.470s	1.339m	1.016ms	3	3	100.00
V2S		TOTAL				30	30	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	45.210s	1.878m	19.649ms	2	5	40.00
V3		TOTAL				2	5	40.00
		TOTAL				258	262	98.47

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
89.92	97.26	81.99	88.25	76.60	94.27	94.27	96.80

Simulation Wall Clock Time

Target	Elapsed
build	00:07:13
run	30:46:43
cov_merge	30:47:37
cov_report	30:47:52
Total	30:47:52

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:1237) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 2.lc_ctrl_stress_all_with_rand_reset.60091265961445394220136171154002816209025667828108340058825513603016536886820
      Line 8851, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1832975721 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1832975721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.lc_ctrl_stress_all_with_rand_reset.29941969398159826742966568796111895293225068289642523138579385674124503966539
      Line 1329, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2368413274 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2368413274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:
  • Test lc_ctrl_jtag_errors has 1 failures.

    • 17.lc_ctrl_jtag_errors.42045444966511258955427478638560520163407564616649389094267062942879885281759
      Line 1771, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_jtag_errors/latest/run.log

        UVM_ERROR @ 3614238470 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 3614238470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---