LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Sunday August 02 2026 00:03:30 UTC

GitHub Revision: 0ff052588e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	2.800s	8.535s	837.797us	1	1	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	0.900s	9.391s	20.878us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	0.840s	9.378s	57.670us	3	3	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.470s	10.250s	68.532us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.010s	10.211s	85.455us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.220s	10.306s	26.423us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	0.840s	9.378s	57.670us	3	3	100.00
		lc_ctrl_csr_aliasing	1.010s	10.211s	85.455us	5	5	100.00
V1		TOTAL				39	39	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	1.690s	7.349s	62.370us	1	1	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	10.030s	23.595s	321.861us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.070s	11.336s	13.239us	8	8	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	1.360s	7.354s	258.848us	1	1	100.00
V2	lc_state_failure	lc_ctrl_state_failure	5.940s	13.350s	1.483ms	3	3	100.00
V2	lc_errors	lc_ctrl_errors	7.010s	15.410s	4.038ms	4	4	100.00
V2	security_escalation	lc_ctrl_state_failure	5.940s	13.350s	1.483ms	3	3	100.00
		lc_ctrl_prog_failure	1.360s	7.354s	258.848us	1	1	100.00
		lc_ctrl_errors	7.010s	15.410s	4.038ms	4	4	100.00
		lc_ctrl_security_escalation	6.840s	15.437s	844.049us	5	5	100.00
		lc_ctrl_jtag_state_failure	43.650s	52.776s	6.115ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	9.090s	17.539s	1.127ms	3	3	100.00
		lc_ctrl_jtag_errors	32.360s	37.196s	2.333ms	2	3	66.67
V2	jtag_access	lc_ctrl_jtag_smoke	6.460s	15.316s	852.897us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	16.080s	26.871s	3.913ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	9.090s	17.539s	1.127ms	3	3	100.00
		lc_ctrl_jtag_errors	32.360s	37.196s	2.333ms	2	3	66.67
		lc_ctrl_jtag_access	6.100s	11.368s	1.740ms	3	3	100.00
		lc_ctrl_jtag_regwen_during_op	23.400s	33.919s	2.144ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	1.590s	12.556s	92.870us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.360s	12.556s	1.779ms	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	22.260s	28.812s	8.609ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	12.650s	16.338s	4.977ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.140s	12.383s	93.936us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	2.330s	12.385s	464.452us	3	3	100.00
		lc_ctrl_jtag_alert_test	1.820s	10.406s	333.994us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	16.750s	25.988s	6.076ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	0.800s	8.224s	16.927us	3	3	100.00
V2	stress_all	lc_ctrl_stress_all	5.075m	5.219m	60.868ms	6	6	100.00
V2	alert_test	lc_ctrl_alert_test	1.260s	10.298s	70.867us	3	3	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	3.000s	12.490s	289.847us	3	3	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	3.000s	12.490s	289.847us	3	3	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	0.900s	9.391s	20.878us	5	5	100.00
		lc_ctrl_csr_rw	0.840s	9.378s	57.670us	3	3	100.00
		lc_ctrl_csr_aliasing	1.010s	10.211s	85.455us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.040s	10.389s	72.320us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	0.900s	9.391s	20.878us	5	5	100.00
		lc_ctrl_csr_rw	0.840s	9.378s	57.670us	3	3	100.00
		lc_ctrl_csr_aliasing	1.010s	10.211s	85.455us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.040s	10.389s	72.320us	20	20	100.00
V2		TOTAL				218	219	99.54
V2S	tl_intg_err	lc_ctrl_sec_cm	5.670s	14.383s	1.373ms	3	3	100.00
		lc_ctrl_tl_intg_err	2.040s	10.405s	119.343us	18	18	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	2.040s	10.405s	119.343us	18	18	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	10.030s	23.595s	321.861us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	5.940s	13.350s	1.483ms	3	3	100.00
		lc_ctrl_sec_cm	5.670s	14.383s	1.373ms	3	3	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	5.940s	13.350s	1.483ms	3	3	100.00
		lc_ctrl_sec_cm	5.670s	14.383s	1.373ms	3	3	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	5.940s	13.350s	1.483ms	3	3	100.00
		lc_ctrl_sec_cm	5.670s	14.383s	1.373ms	3	3	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	5.940s	13.350s	1.483ms	3	3	100.00
		lc_ctrl_sec_cm	5.670s	14.383s	1.373ms	3	3	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	5.940s	13.350s	1.483ms	3	3	100.00
		lc_ctrl_sec_cm	5.670s	14.383s	1.373ms	3	3	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	5.940s	13.350s	1.483ms	3	3	100.00
		lc_ctrl_sec_cm	5.670s	14.383s	1.373ms	3	3	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	5.940s	13.350s	1.483ms	3	3	100.00
		lc_ctrl_sec_cm	5.670s	14.383s	1.373ms	3	3	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	5.940s	13.350s	1.483ms	3	3	100.00
		lc_ctrl_sec_cm	5.670s	14.383s	1.373ms	3	3	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	6.840s	15.437s	844.049us	5	5	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	1.690s	7.349s	62.370us	1	1	100.00
		lc_ctrl_jtag_state_post_trans	16.080s	26.871s	3.913ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	5.660s	14.439s	563.185us	5	5	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	5.660s	14.439s	563.185us	5	5	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	3.630s	8.259s	1.059ms	1	1	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	5.860s	13.382s	364.012us	3	3	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	5.860s	13.382s	364.012us	3	3	100.00
V2S		TOTAL				30	30	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	57.340s	1.098m	3.823ms	6	9	66.67
V3		TOTAL				6	9	66.67
		TOTAL				293	297	98.65

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
89.96	97.24	82.18	88.25	76.84	94.36	94.41	96.44

Simulation Wall Clock Time

Target	Elapsed
build	00:07:13
run	30:46:43
cov_merge	30:47:37
cov_report	30:47:52
Total	30:47:52

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:1237) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 5.lc_ctrl_stress_all_with_rand_reset.24874912917810034247283865394172992345008436651373067169875864908732050871242
      Line 405, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4233268999 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 4233268999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 7.lc_ctrl_stress_all_with_rand_reset.61335679200210746763794219404320266004344577672503165094751342972792013366777
      Line 6131, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2535160086 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2535160086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:
  • Test lc_ctrl_jtag_errors has 1 failures.

    • 2.lc_ctrl_jtag_errors.78659502333372045122968044969911744045601318511513883554621666464517900026295
      Line 1361, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_errors/latest/run.log

        UVM_ERROR @ 981461510 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 981461510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---