0ff052588e| Stage | Name | Tests | Max Job Runtime | Max Wall Clock | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|---|
| V1 | mbx_smoke | mbx_smoke | 42.720s | 51.997s | 2.574ms | 3 | 3 | 100.00 |
| V1 | csr_hw_reset | mbx_csr_hw_reset | 0.890s | 35.320s | 17.863us | 5 | 5 | 100.00 |
| V1 | csr_rw | mbx_csr_rw | 0.860s | 35.318s | 32.524us | 3 | 3 | 100.00 |
| V1 | csr_bit_bash | mbx_csr_bit_bash | 2.460s | 36.281s | 931.642us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | mbx_csr_aliasing | 0.910s | 35.290s | 24.488us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | mbx_csr_mem_rw_with_rand_reset | 1.380s | 26.248s | 82.362us | 1 | 4 | 25.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | mbx_csr_rw | 0.860s | 35.318s | 32.524us | 3 | 3 | 100.00 |
| mbx_csr_aliasing | 0.910s | 35.290s | 24.488us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 22 | 25 | 88.00 | ||||
| V2 | mbx_stress | mbx_stress | 4.320s | 8.187s | 915.408us | 0 | 1 | 0.00 |
| V2 | mbx_max_activity | mbx_stress_zero_delays | 2.690s | 7.168s | 489.191us | 0 | 1 | 0.00 |
| V2 | mbx_stress_all | mbx_stress_all | 0 | 0 | -- | |||
| V2 | mbx_imbx_oob | mbx_imbx_oob | 39.670s | 48.037s | 17.805ms | 3 | 4 | 75.00 |
| V2 | mbx_range_lock | 0 | 0 | -- | ||||
| V2 | mbx_doe_intr_msg | mbx_doe_intr_msg | 12.030s | 20.441s | 1.084ms | 3 | 3 | 100.00 |
| V2 | alert_test | mbx_alert_test | 0.640s | 9.226s | 24.850us | 3 | 3 | 100.00 |
| V2 | intr_test | mbx_intr_test | 0.880s | 36.321s | 153.410us | 8 | 8 | 100.00 |
| V2 | tl_d_oob_addr_access | mbx_tl_errors | 1.910s | 56.360s | 58.881us | 2 | 5 | 40.00 |
| V2 | tl_d_illegal_access | mbx_tl_errors | 1.910s | 56.360s | 58.881us | 2 | 5 | 40.00 |
| V2 | tl_d_outstanding_access | mbx_csr_hw_reset | 0.890s | 35.320s | 17.863us | 5 | 5 | 100.00 |
| mbx_csr_rw | 0.860s | 35.318s | 32.524us | 3 | 3 | 100.00 | ||
| mbx_csr_aliasing | 0.910s | 35.290s | 24.488us | 5 | 5 | 100.00 | ||
| mbx_same_csr_outstanding | 1.060s | 30.224s | 65.767us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | mbx_csr_hw_reset | 0.890s | 35.320s | 17.863us | 5 | 5 | 100.00 |
| mbx_csr_rw | 0.860s | 35.318s | 32.524us | 3 | 3 | 100.00 | ||
| mbx_csr_aliasing | 0.910s | 35.290s | 24.488us | 5 | 5 | 100.00 | ||
| mbx_same_csr_outstanding | 1.060s | 30.224s | 65.767us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 39 | 45 | 86.67 | ||||
| V2S | tl_intg_err | mbx_tl_intg_err | 5.480s | 53.344s | 3.761ms | 10 | 10 | 100.00 |
| mbx_sec_cm | 0.760s | 9.213s | 34.091us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | sec_cm_bus_integrity | 0 | 0 | -- | |||
| V2S | sec_cm_address_range_config_regwen_mubi | sec_cm_address_range_config_regwen_mubi | 0 | 0 | -- | |||
| V2S | TOTAL | 15 | 15 | 100.00 | ||||
| V3 | stress_all_with_rand_reset | mbx_stress_all_with_rand_reset | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 0 | -- | ||||
| TOTAL | 76 | 85 | 89.41 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 5 | 83.33 |
| V2 | 10 | 8 | 4 | 40.00 |
| V2S | 4 | 2 | 2 | 50.00 |
| V3 | 1 | 0 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 85.11 | 95.76 | 90.78 | 82.06 | 47.37 | 90.83 | 97.15 | 91.84 |
| Target | Elapsed |
|---|---|
| build | 00:07:13 |
| run | 30:46:43 |
| cov_merge | 30:47:37 |
| cov_report | 30:47:52 |
| Total | 30:47:52 |
UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register has 3 failures:
Test mbx_stress has 1 failures.
0.mbx_stress.69383187304166353525973050914386611978343548625156639248718784523974181863996
Line 185, in log /home/runner/_work/pavona/pavona/scratch/main/mbx-sim-vcs/0.mbx_stress/latest/run.log
UVM_ERROR @ 915407728 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
UVM_INFO @ 915407728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test mbx_stress_zero_delays has 1 failures.
0.mbx_stress_zero_delays.111316578950999862265241062246119586919213648271679183466719572557491117301221
Line 240, in log /home/runner/_work/pavona/pavona/scratch/main/mbx-sim-vcs/0.mbx_stress_zero_delays/latest/run.log
UVM_ERROR @ 489190603 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
UVM_INFO @ 489190603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test mbx_imbx_oob has 1 failures.
1.mbx_imbx_oob.30337997521552391948096243004633119719302576142389346470105779842933270686420
Line 87, in log /home/runner/_work/pavona/pavona/scratch/main/mbx-sim-vcs/1.mbx_imbx_oob/latest/run.log
UVM_ERROR @ 105166332 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
UVM_INFO @ 105166332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:563) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface mbx_soc_reg_block, TL item: req: (cip_tl_seq_item@8291) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * a_blocked: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
1.mbx_csr_mem_rw_with_rand_reset.4549381481973269981770896468177789086907283841720848525162790444739373339318
Line 85, in log /home/runner/_work/pavona/pavona/scratch/main/mbx-sim-vcs/1.mbx_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 5821136 ps: (cip_base_scoreboard.sv:563) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface mbx_soc_reg_block, TL item: req: (cip_tl_seq_item@8291) { a_addr: 'h9191d2f4 a_data: 'h4eaf76af a_mask: 'h2 a_size: 'h2 a_param: 'h0 a_source: 'hda a_opcode: 'h1 a_user: 'h250fe a_blocked: 'h0 d_param: 'h0 d_source: 'hda d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 1, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0 trans_blocked: 0
UVM_INFO @ 5821136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:563) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface mbx_soc_reg_block, TL item: req: (cip_tl_seq_item@4089) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * a_blocked: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
2.mbx_tl_errors.95535251242360515621712127647962591888805367390261757416730336804655090941685
Line 79, in log /home/runner/_work/pavona/pavona/scratch/main/mbx-sim-vcs/2.mbx_tl_errors/latest/run.log
UVM_ERROR @ 11280525 ps: (cip_base_scoreboard.sv:563) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface mbx_soc_reg_block, TL item: req: (cip_tl_seq_item@4089) { a_addr: 'hb2c4afb0 a_data: 'hd2abb7d9 a_mask: 'hb a_size: 'h2 a_param: 'h0 a_source: 'hae a_opcode: 'h1 a_user: 'h26038 a_blocked: 'h0 d_param: 'h0 d_source: 'hae d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 1, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0 trans_blocked: 0
UVM_INFO @ 11280525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:563) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface mbx_soc_reg_block, TL item: req: (cip_tl_seq_item@12391) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * a_blocked: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
2.mbx_csr_mem_rw_with_rand_reset.34293492200299491801227851591677122417752115499803916006903273452618967750723
Line 80, in log /home/runner/_work/pavona/pavona/scratch/main/mbx-sim-vcs/2.mbx_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 13256424 ps: (cip_base_scoreboard.sv:563) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface mbx_soc_reg_block, TL item: req: (cip_tl_seq_item@12391) { a_addr: 'h9ca0f454 a_data: 'h5b69da3b a_mask: 'h8 a_size: 'h2 a_param: 'h0 a_source: 'h64 a_opcode: 'h1 a_user: 'h26492 a_blocked: 'h0 d_param: 'h0 d_source: 'h64 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 1, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0 trans_blocked: 0
UVM_INFO @ 13256424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:563) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface mbx_soc_reg_block, TL item: req: (cip_tl_seq_item@4147) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * a_blocked: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
3.mbx_tl_errors.7276797931152434607793392574510846461909466764520077314245327769652435874420
Line 79, in log /home/runner/_work/pavona/pavona/scratch/main/mbx-sim-vcs/3.mbx_tl_errors/latest/run.log
UVM_ERROR @ 3002299 ps: (cip_base_scoreboard.sv:563) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface mbx_soc_reg_block, TL item: req: (cip_tl_seq_item@4147) { a_addr: 'hc4c82b54 a_data: 'h465c0cb5 a_mask: 'hc a_size: 'h2 a_param: 'h0 a_source: 'h7c a_opcode: 'h1 a_user: 'h25646 a_blocked: 'h0 d_param: 'h0 d_source: 'h7c d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 1, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0 trans_blocked: 0
UVM_INFO @ 3002299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:563) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface mbx_soc_reg_block, TL item: req: (cip_tl_seq_item@8783) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * a_blocked: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
3.mbx_csr_mem_rw_with_rand_reset.32931377052967400764282470101269040788992844606182111238261665450266179490944
Line 80, in log /home/runner/_work/pavona/pavona/scratch/main/mbx-sim-vcs/3.mbx_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 15432163 ps: (cip_base_scoreboard.sv:563) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface mbx_soc_reg_block, TL item: req: (cip_tl_seq_item@8783) { a_addr: 'hbaf248b4 a_data: 'h15668566 a_mask: 'h1 a_size: 'h0 a_param: 'h0 a_source: 'hac a_opcode: 'h1 a_user: 'h275be a_blocked: 'h0 d_param: 'h0 d_source: 'hac d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h152a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 1, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0 trans_blocked: 0
UVM_INFO @ 15432163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:563) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface mbx_soc_reg_block, TL item: req: (cip_tl_seq_item@11045) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * a_blocked: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
4.mbx_tl_errors.82480338052572389749402309231129123023455192039101389541945539320036269904691
Line 79, in log /home/runner/_work/pavona/pavona/scratch/main/mbx-sim-vcs/4.mbx_tl_errors/latest/run.log
UVM_ERROR @ 14546075 ps: (cip_base_scoreboard.sv:563) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface mbx_soc_reg_block, TL item: req: (cip_tl_seq_item@11045) { a_addr: 'h866e3270 a_data: 'h53303f4b a_mask: 'h9 a_size: 'h2 a_param: 'h0 a_source: 'h1 a_opcode: 'h1 a_user: 'h27d8b a_blocked: 'h0 d_param: 'h0 d_source: 'h1 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 1, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0 trans_blocked: 0
UVM_INFO @ 14546075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---