OTP_CTRL/DRAGONFLY Simulation Results

Sunday August 02 2026 00:03:30 UTC

GitHub Revision: `0ff052588e`

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.230s	12.092s	54.080us	1	1	100.00
V1	smoke	otp_ctrl_smoke	3.950s	15.079s	1.829ms	1	1	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	3.150s	1.404m	535.182us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	1.860s	1.387m	175.922us	3	3	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	6.560s	1.454m	791.559us	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	10.220s	1.521m	2.191ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	3.570s	50.196s	358.780us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	1.860s	1.387m	175.922us	3	3	100.00
		otp_ctrl_csr_aliasing	10.220s	1.521m	2.191ms	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.800s	1.322m	70.839us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.470s	1.371m	48.726us	5	5	100.00
V1		TOTAL				50	50	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	1.487m	1.672m	5.956ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	6.580s	58.374s	2.290ms	52	52	100.00
V2	partition_check	otp_ctrl_background_chks	36.800s	1.356m	19.914ms	10	10	100.00
		otp_ctrl_check_fail	45.340s	1.340m	12.025ms	19	20	95.00
V2	regwen_during_otp_init	otp_ctrl_regwen	10.640s	51.181s	765.660us	17	17	100.00
V2	partition_lock	otp_ctrl_dai_lock	15.310s	30.080s	926.123us	1	1	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	24.190s	45.111s	1.523ms	1	1	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	28.720s	57.184s	16.026ms	4	4	100.00
		otp_ctrl_parallel_lc_esc	20.490s	1.123m	6.968ms	24	24	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	24.770s	1.002m	19.550ms	4	4	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.284m	1.638m	21.453ms	15	17	88.24
V2	test_access	otp_ctrl_test_access	22.090s	51.162s	1.305ms	3	3	100.00
V2	stress_all	otp_ctrl_stress_all	14.916m	15.505m	356.128ms	26	26	100.00
V2	intr_test	otp_ctrl_intr_test	2.090s	1.389m	50.553us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	2.320s	37.124s	91.560us	3	3	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	6.050s	1.456m	546.250us	4	4	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	6.050s	1.456m	546.250us	4	4	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	3.150s	1.404m	535.182us	5	5	100.00
		otp_ctrl_csr_rw	1.860s	1.387m	175.922us	3	3	100.00
		otp_ctrl_csr_aliasing	10.220s	1.521m	2.191ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.440s	50.195s	2.703ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	3.150s	1.404m	535.182us	5	5	100.00
		otp_ctrl_csr_rw	1.860s	1.387m	175.922us	3	3	100.00
		otp_ctrl_csr_aliasing	10.220s	1.521m	2.191ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.440s	50.195s	2.703ms	20	20	100.00
V2		TOTAL				254	257	98.83
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	5.072m	5.753m	78.106ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	5.072m	5.753m	78.106ms	5	5	100.00
		otp_ctrl_tl_intg_err	22.830s	1.673m	6.661ms	6	6	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	5.072m	5.753m	78.106ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	5.072m	5.753m	78.106ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	22.830s	1.673m	6.661ms	6	6	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	3.950s	15.079s	1.829ms	1	1	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	3.950s	15.079s	1.829ms	1	1	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	5.072m	5.753m	78.106ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	5.072m	5.753m	78.106ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	5.072m	5.753m	78.106ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	5.072m	5.753m	78.106ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	5.072m	5.753m	78.106ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	5.072m	5.753m	78.106ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	5.072m	5.753m	78.106ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	5.072m	5.753m	78.106ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	5.072m	5.753m	78.106ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	5.072m	5.753m	78.106ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	5.072m	5.753m	78.106ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	5.072m	5.753m	78.106ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	5.072m	5.753m	78.106ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	5.072m	5.753m	78.106ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	5.072m	5.753m	78.106ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	20.490s	1.123m	6.968ms	24	24	100.00
		otp_ctrl_sec_cm	5.072m	5.753m	78.106ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	20.490s	1.123m	6.968ms	24	24	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	20.490s	1.123m	6.968ms	24	24	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	20.490s	1.123m	6.968ms	24	24	100.00
		otp_ctrl_macro_errs	1.284m	1.638m	21.453ms	15	17	88.24
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	20.490s	1.123m	6.968ms	24	24	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	20.490s	1.123m	6.968ms	24	24	100.00
		otp_ctrl_sec_cm	5.072m	5.753m	78.106ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	20.490s	1.123m	6.968ms	24	24	100.00
		otp_ctrl_sec_cm	5.072m	5.753m	78.106ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	20.490s	1.123m	6.968ms	24	24	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	20.490s	1.123m	6.968ms	24	24	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	20.490s	1.123m	6.968ms	24	24	100.00
		otp_ctrl_macro_errs	1.284m	1.638m	21.453ms	15	17	88.24
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	20.490s	1.123m	6.968ms	24	24	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	20.490s	1.123m	6.968ms	24	24	100.00
		otp_ctrl_sec_cm	5.072m	5.753m	78.106ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	6.580s	58.374s	2.290ms	52	52	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	45.340s	1.340m	12.025ms	19	20	95.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	15.310s	30.080s	926.123us	1	1	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	15.310s	30.080s	926.123us	1	1	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	15.310s	30.080s	926.123us	1	1	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	15.310s	30.080s	926.123us	1	1	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	15.310s	30.080s	926.123us	1	1	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	3.950s	15.079s	1.829ms	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	15.310s	30.080s	926.123us	1	1	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	3.950s	15.079s	1.829ms	1	1	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	5.072m	5.753m	78.106ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	10.640s	51.181s	765.660us	17	17	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	3.950s	15.079s	1.829ms	1	1	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	3.950s	15.079s	1.829ms	1	1	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.284m	1.638m	21.453ms	15	17	88.24
V2S		TOTAL				11	11	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	1.347m	1.571m	28.530ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	3.326m	3.887m	46.842ms	18	20	90.00
V3		TOTAL				19	21	90.48
	Unmapped tests	otp_ctrl_zeroization	5.760s	45.190s	3.639ms	14	14	100.00
		otp_ctrl_zeroization_with_checks	10.240s	58.378s	4.260ms	20	20	100.00
		TOTAL				368	373	98.66

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	2	2	2	100.00
V1	9	9	9	100.00
V2	17	17	15	88.24
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
87.77	95.00	93.62	93.04	60.19	93.48	93.40	85.66

Simulation Wall Clock Time

Target	Elapsed
build	00:07:13
run	30:46:43
cov_merge	30:47:37
cov_report	30:47:52
Total	30:47:52

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1664) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 3 failures:

Test otp_ctrl_macro_errs has 2 failures.

11.otp_ctrl_macro_errs.52784066377741671820259842160943660744893265358690523467015632400730255996965
Line 103, in log /home/runner/_work/pavona/pavona/scratch/main/otp_ctrl_top_dragonfly-sim-vcs/11.otp_ctrl_macro_errs/latest/run.log

  UVM_ERROR @ 308100026 ps: (otp_ctrl_scoreboard.sv:1664) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 32768 [0x8000]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 308100026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

15.otp_ctrl_macro_errs.111852972536898565716766414490584719690635050791692860685177563325425697529751
Line 108, in log /home/runner/_work/pavona/pavona/scratch/main/otp_ctrl_top_dragonfly-sim-vcs/15.otp_ctrl_macro_errs/latest/run.log

  UVM_ERROR @ 2945924027 ps: (otp_ctrl_scoreboard.sv:1664) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 4096 [0x1000]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 2945924027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otp_ctrl_check_fail has 1 failures.

15.otp_ctrl_check_fail.806361390547935671298470099634827856624932773465795695329840056458600283077
Line 100, in log /home/runner/_work/pavona/pavona/scratch/main/otp_ctrl_top_dragonfly-sim-vcs/15.otp_ctrl_check_fail/latest/run.log

  UVM_ERROR @ 973413912 ps: (otp_ctrl_scoreboard.sv:1664) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 4096 [0x1000]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 973413912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (otp_ctrl_scoreboard.sv:1664) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 16.otp_ctrl_stress_all_with_rand_reset.73392650632404075760872689130014471601488816348744588021457268481510115406498
    Line 166, in log /home/runner/_work/pavona/pavona/scratch/main/otp_ctrl_top_dragonfly-sim-vcs/16.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 12469496652 ps: (otp_ctrl_scoreboard.sv:1664) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
  UVM_INFO @ 12469496652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:617) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 17.otp_ctrl_stress_all_with_rand_reset.26139388032113852982780891891755228688472142300943041421300745593614438780790
    Line 200, in log /home/runner/_work/pavona/pavona/scratch/main/otp_ctrl_top_dragonfly-sim-vcs/17.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5435787355 ps: (cip_base_scoreboard.sv:617) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
  UVM_INFO @ 5435787355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```