OTP_CTRL/EGRET Simulation Results

Sunday August 02 2026 00:03:30 UTC

GitHub Revision: 0ff052588e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.760s	17.118s	714.932us	3	3	100.00
V1	smoke	otp_ctrl_smoke	2.520s	7.060s	501.486us	1	1	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.590s	11.094s	1.548ms	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	1.330s	10.090s	180.136us	3	3	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	6.930s	16.121s	4.319ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	2.910s	11.093s	158.102us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	2.530s	11.117s	1.028ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	1.330s	10.090s	180.136us	3	3	100.00
		otp_ctrl_csr_aliasing	2.910s	11.093s	158.102us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.280s	6.051s	476.758us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.010s	9.079s	74.385us	5	5	100.00
V1		TOTAL				52	52	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	9.270s	15.101s	628.055us	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	6.060s	38.113s	1.819ms	35	35	100.00
V2	partition_check	otp_ctrl_background_chks	18.680s	45.141s	4.521ms	10	10	100.00
		otp_ctrl_check_fail	30.350s	41.290s	7.565ms	12	12	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	8.590s	38.129s	3.919ms	8	8	100.00
V2	partition_lock	otp_ctrl_dai_lock	12.290s	21.126s	13.680ms	3	3	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	17.260s	27.167s	1.654ms	3	3	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	9.520s	15.088s	677.991us	1	1	100.00
		otp_ctrl_parallel_lc_esc	20.030s	41.394s	1.149ms	11	11	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	21.840s	31.219s	1.498ms	4	4	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	20.650s	54.221s	2.110ms	7	7	100.00
V2	test_access	otp_ctrl_test_access	27.410s	45.207s	21.435ms	3	3	100.00
V2	stress_all	otp_ctrl_stress_all	3.178m	3.659m	41.118ms	16	16	100.00
V2	intr_test	otp_ctrl_intr_test	1.520s	10.106s	492.453us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	2.960s	18.090s	959.424us	3	3	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	4.890s	14.146s	2.664ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	4.890s	14.146s	2.664ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.590s	11.094s	1.548ms	5	5	100.00
		otp_ctrl_csr_rw	1.330s	10.090s	180.136us	3	3	100.00
		otp_ctrl_csr_aliasing	2.910s	11.093s	158.102us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.470s	11.113s	1.917ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.590s	11.094s	1.548ms	5	5	100.00
		otp_ctrl_csr_rw	1.330s	10.090s	180.136us	3	3	100.00
		otp_ctrl_csr_aliasing	2.910s	11.093s	158.102us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.470s	11.113s	1.917ms	20	20	100.00
V2		TOTAL				207	207	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	2.968m	3.387m	94.577ms	5	6	83.33
V2S	tl_intg_err	otp_ctrl_sec_cm	2.968m	3.387m	94.577ms	5	6	83.33
		otp_ctrl_tl_intg_err	23.660s	28.240s	19.141ms	13	13	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	2.968m	3.387m	94.577ms	5	6	83.33
V2S	prim_fsm_check	otp_ctrl_sec_cm	2.968m	3.387m	94.577ms	5	6	83.33
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	23.660s	28.240s	19.141ms	13	13	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	2.520s	7.060s	501.486us	1	1	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	2.520s	7.060s	501.486us	1	1	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	2.968m	3.387m	94.577ms	5	6	83.33
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	2.968m	3.387m	94.577ms	5	6	83.33
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	2.968m	3.387m	94.577ms	5	6	83.33
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	2.968m	3.387m	94.577ms	5	6	83.33
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	2.968m	3.387m	94.577ms	5	6	83.33
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	2.968m	3.387m	94.577ms	5	6	83.33
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	2.968m	3.387m	94.577ms	5	6	83.33
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	2.968m	3.387m	94.577ms	5	6	83.33
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	2.968m	3.387m	94.577ms	5	6	83.33
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	2.968m	3.387m	94.577ms	5	6	83.33
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	2.968m	3.387m	94.577ms	5	6	83.33
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	2.968m	3.387m	94.577ms	5	6	83.33
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	2.968m	3.387m	94.577ms	5	6	83.33
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	2.968m	3.387m	94.577ms	5	6	83.33
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	2.968m	3.387m	94.577ms	5	6	83.33
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	20.030s	41.394s	1.149ms	11	11	100.00
		otp_ctrl_sec_cm	2.968m	3.387m	94.577ms	5	6	83.33
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	20.030s	41.394s	1.149ms	11	11	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	20.030s	41.394s	1.149ms	11	11	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	20.030s	41.394s	1.149ms	11	11	100.00
		otp_ctrl_macro_errs	20.650s	54.221s	2.110ms	7	7	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	20.030s	41.394s	1.149ms	11	11	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	20.030s	41.394s	1.149ms	11	11	100.00
		otp_ctrl_sec_cm	2.968m	3.387m	94.577ms	5	6	83.33
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	20.030s	41.394s	1.149ms	11	11	100.00
		otp_ctrl_sec_cm	2.968m	3.387m	94.577ms	5	6	83.33
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	20.030s	41.394s	1.149ms	11	11	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	20.030s	41.394s	1.149ms	11	11	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	20.030s	41.394s	1.149ms	11	11	100.00
		otp_ctrl_macro_errs	20.650s	54.221s	2.110ms	7	7	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	20.030s	41.394s	1.149ms	11	11	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	20.030s	41.394s	1.149ms	11	11	100.00
		otp_ctrl_sec_cm	2.968m	3.387m	94.577ms	5	6	83.33
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	6.060s	38.113s	1.819ms	35	35	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	30.350s	41.290s	7.565ms	12	12	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	12.290s	21.126s	13.680ms	3	3	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	12.290s	21.126s	13.680ms	3	3	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	12.290s	21.126s	13.680ms	3	3	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	12.290s	21.126s	13.680ms	3	3	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	12.290s	21.126s	13.680ms	3	3	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	2.520s	7.060s	501.486us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	12.290s	21.126s	13.680ms	3	3	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	2.520s	7.060s	501.486us	1	1	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	2.968m	3.387m	94.577ms	5	6	83.33
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	8.590s	38.129s	3.919ms	8	8	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	2.520s	7.060s	501.486us	1	1	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	2.520s	7.060s	501.486us	1	1	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	20.650s	54.221s	2.110ms	7	7	100.00
V2S		TOTAL				18	19	94.74
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	7.680s	13.074s	2.985ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	2.295m	2.516m	52.538ms	10	12	83.33
V3		TOTAL				11	13	84.62
	Unmapped tests	otp_ctrl_zeroization	4.300s	38.110s	464.622us	6	6	100.00
		otp_ctrl_zeroization_with_checks	7.240s	22.124s	973.925us	3	3	100.00
		TOTAL				297	300	99.00

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	2	2	2	100.00
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	1	50.00
V3	2	2	1	50.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
88.47	90.61	94.65	96.03	63.89	86.99	94.75	92.40

Simulation Wall Clock Time

Target	Elapsed
build	00:07:13
run	30:46:43
cov_merge	30:47:37
cov_report	30:47:52
Total	30:47:52

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:1023) virtual_sequencer [otp_ctrl_common_vseq] expect alert:fatal_check_error to fire has 1 failures:

  • Test otp_ctrl_sec_cm has 1 failures.

    • 5.otp_ctrl_sec_cm.100281473539360952524780423188871599204791554427560797417669886919580553246091
      Line 1504, in log /home/runner/_work/pavona/pavona/scratch/main/otp_ctrl_top_egret-sim-vcs/5.otp_ctrl_sec_cm/latest/run.log

        UVM_ERROR @ 94576699934 ps: (cip_base_vseq.sv:1023) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] expect alert:fatal_check_error to fire
        UVM_INFO @ 94576699934 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_scoreboard.sv:1352) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 9.otp_ctrl_stress_all_with_rand_reset.21725384650633172924094897492843030469155041245899409502290570040418626987946
      Line 135, in log /home/runner/_work/pavona/pavona/scratch/main/otp_ctrl_top_egret-sim-vcs/9.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1775130286 ps: (otp_ctrl_scoreboard.sv:1352) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
        UVM_INFO @ 1775130286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_scoreboard.sv:1352) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 10.otp_ctrl_stress_all_with_rand_reset.113836771894951882961200218623232462686796695958216716182115084544029443855061
      Line 102, in log /home/runner/_work/pavona/pavona/scratch/main/otp_ctrl_top_egret-sim-vcs/10.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  38652815 ps: (otp_ctrl_scoreboard.sv:1352) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2558238021 [0x987b9d45] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @  38652815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---