PATTGEN Simulation Results

Sunday August 02 2026 00:03:30 UTC

GitHub Revision: `0ff052588e`

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	1.950s	10.080s	96.932us	5	5	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	0.800s	22.085s	22.050us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	0.790s	27.089s	19.158us	7	7	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	2.300s	20.084s	191.842us	3	3	100.00
V1	csr_aliasing	pattgen_csr_aliasing	0.850s	22.086s	101.208us	4	4	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	0.990s	22.073s	28.367us	7	7	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	0.790s	27.089s	19.158us	7	7	100.00
		pattgen_csr_aliasing	0.850s	22.086s	101.208us	4	4	100.00
V1		TOTAL				31	31	100.00
V2	perf	pattgen_perf	17.535m	17.603m	600.000ms	1	3	33.33
V2	cnt_rollover	cnt_rollover	41.170s	45.336s	8.049ms	5	5	100.00
V2	error	pattgen_error	0.650s	5.129s	21.726us	1	1	100.00
V2	stress_all	pattgen_stress_all	2.248h	2.251h	4.399s	6	8	75.00
V2	alert_test	pattgen_alert_test	0.500s	5.127s	17.943us	3	3	100.00
V2	intr_test	pattgen_intr_test	0.770s	36.103s	17.078us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	2.040s	35.096s	222.631us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	2.040s	35.096s	222.631us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	0.800s	22.085s	22.050us	5	5	100.00
		pattgen_csr_rw	0.790s	27.089s	19.158us	7	7	100.00
		pattgen_csr_aliasing	0.850s	22.086s	101.208us	4	4	100.00
		pattgen_same_csr_outstanding	0.920s	22.068s	16.110us	23	23	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	0.800s	22.085s	22.050us	5	5	100.00
		pattgen_csr_rw	0.790s	27.089s	19.158us	7	7	100.00
		pattgen_csr_aliasing	0.850s	22.086s	101.208us	4	4	100.00
		pattgen_same_csr_outstanding	0.920s	22.068s	16.110us	23	23	100.00
V2		TOTAL				109	113	96.46
V2S	tl_intg_err	pattgen_tl_intg_err	1.360s	35.103s	81.944us	50	50	100.00
		pattgen_sec_cm	0.770s	9.083s	135.212us	3	3	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	1.360s	35.103s	81.944us	50	50	100.00
V2S		TOTAL				53	53	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	1.243m	1.390m	15.556ms	1	3	33.33
V3		TOTAL				1	3	33.33
	Unmapped tests	pattgen_inactive_level	7.410s	11.095s	10.212ms	4	5	80.00
		TOTAL				198	205	96.59

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	6	75.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.96	99.82	99.52	100.00	--	100.00	96.95	67.50

Simulation Wall Clock Time

Target	Elapsed
build	00:07:13
run	30:46:43
cov_merge	30:47:37
cov_report	30:47:52
Total	30:47:52

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test pattgen_perf has 2 failures.
  - 1.pattgen_perf.46565066683523250461665414743682073144820096869267165525746433658315500432423
    Line 106, in log /home/runner/_work/pavona/pavona/scratch/main/pattgen-sim-vcs/1.pattgen_perf/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.pattgen_perf.71138209659780953665071886097908650817528467854845240029755590411368632324797
    Line 106, in log /home/runner/_work/pavona/pavona/scratch/main/pattgen-sim-vcs/2.pattgen_perf/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_vseq.sv:1237) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

Test pattgen_stress_all_with_rand_reset has 2 failures.

1.pattgen_stress_all_with_rand_reset.39876394317406703481762746713681862916216986675216772995466291955903195093517
Line 159, in log /home/runner/_work/pavona/pavona/scratch/main/pattgen-sim-vcs/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4307356731 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 4307397780 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 4307397780 ps: (cip_base_vseq.sv:1154) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 1/5
  UVM_INFO @ 4307647779 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

2.pattgen_stress_all_with_rand_reset.30820480784926729759968680114275579176812958873523585420088617364826127866202
Line 197, in log /home/runner/_work/pavona/pavona/scratch/main/pattgen-sim-vcs/2.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1381948098 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 1381972396 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1381972396 ps: (cip_base_vseq.sv:1154) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 1/10
  UVM_INFO @ 1382258108 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 2.pattgen_inactive_level.26659161007125904896233064934852186502276721832293499796696241245711928622361
    Line 106, in log /home/runner/_work/pavona/pavona/scratch/main/pattgen-sim-vcs/2.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10211930069 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x1d16c950, Comparison=CompareOpEq, exp_data=0x0, call_count=5)
  UVM_INFO @ 10211930069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (pattgen_scoreboard.sv:262) scoreboard [scoreboard] has 1 failures:
- Test pattgen_stress_all has 1 failures.
  - 5.pattgen_stress_all.17471062147639312173904962784899889830329734869042658994956207273812719860175
    Line 177, in log /home/runner/_work/pavona/pavona/scratch/main/pattgen-sim-vcs/5.pattgen_stress_all/latest/run.log
```
  UVM_ERROR @ 180044655 ps: (pattgen_scoreboard.sv:262) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: has 1 failures:
- Test pattgen_stress_all has 1 failures.
  - 6.pattgen_stress_all.84165178888807608098662393596081866760158740532878737264181491965043846020676
    Line 189, in log /home/runner/_work/pavona/pavona/scratch/main/pattgen-sim-vcs/6.pattgen_stress_all/latest/run.log
```
  UVM_ERROR @ 4399465120548 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
  -------------------------------------
  Name      Type          Size  Value
  -------------------------------------
  exp_item  pattgen_item  -     @378844
```