PRIM_ESC Simulation Results

Sunday August 02 2026 00:03:30 UTC

GitHub Revision: 0ff052588e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	prim_esc_request_test	prim_esc_test	0.610s	1.886m	4.899us	9	9	100.00
V1	prim_ping_req_interrupted_by_esc_req_test	prim_esc_test	0.610s	1.886m	4.899us	9	9	100.00
V1	prim_esc_tx_integrity_errors_test	prim_esc_test	0.610s	1.886m	4.899us	9	9	100.00
V1	prim_esc_reverse_ping_timeout_test	prim_esc_test	0.610s	1.886m	4.899us	9	9	100.00
V1	prim_esc_receiver_counter_fail_test	prim_esc_test	0.610s	1.886m	4.899us	9	9	100.00
V1	prim_esc_handshake_with_rand_reset_test	prim_esc_test	0.610s	1.886m	4.899us	9	9	100.00
V1		TOTAL				9	9	100.00
V2		TOTAL				0	0	--
V2S		TOTAL				0	0	--
V3		TOTAL				0	0	--
		TOTAL				9	9	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	1	1	1	100.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.29	95.41	87.80	100.00	96.43	88.89	85.19

Simulation Wall Clock Time

Target	Elapsed
build	00:07:13
run	30:46:43
cov_merge	30:47:37
cov_report	30:47:52
Total	30:47:52