PRIM_LFSR Simulation Results

Sunday August 02 2026 00:03:30 UTC

GitHub Revision: 0ff052588e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Max Wall Clock Simulated Time Passing Total Pass Rate
V1 TOTAL 0 0 --
V2 TOTAL 0 0 --
V2S TOTAL 0 0 --
V3 TOTAL 0 0 --
Unmapped tests prim_lfsr_fib_smoke 0.920s 6.037s 1.192ms 1 1 100.00
prim_lfsr_gal_smoke 1.220s 1.269m 1.333ms 1 1 100.00
prim_lfsr_fib_test 1.611m 5.410m 336.911ms 3 3 100.00
prim_lfsr_gal_test 2.052m 6.981m 336.872ms 3 3 100.00
TOTAL 8 8 100.00

Testplan Progress

Items Total Written Passing Progress
N.A. 4 4 4 100.00

Coverage Results

SCORE LINE COND TOGGLE FSM BRANCH ASSERT
98.31 100.00 96.55 100.00 -- 100.00 95.00

Simulation Wall Clock Time

Target Elapsed
build 00:07:13
run 30:46:43
cov_merge 30:47:37
cov_report 30:47:52
Total 30:47:52